Hex D Flip-Flop

www.DataSheet4U.com 54AC174 • 54ACT174 Hex D Flip-Flop with Master Reset July 1998 54AC174 • 54ACT174 Hex D Flip-Flop with Master Reset General Description The ’AC/’ACT174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. n Outputs source/sink 24 mA n ’ACT174 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) — ’AC174: 5962-87626 — ’ACT174: 5962-87757 Features n ICC reduced by 50% Logic Symbols Pin Names D0–D5 CP MR Q0–Q5 Description Data Inputs Clock Pulse Input Master Reset Input Outputs DS100277-1 IEEE/IEC DS100277-2 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100277 www.national.com Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100277-4 DS100277-3 Functional Description The ’AC/’ACT174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The ’AC/’ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs MR L H H H CP X N N Output D X H L X Q L H L Q L H = HIGH Voltage Level L = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Logic Diagram DS100277-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns ±50 mA ±50 mA −65˚C to +150˚C 175˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 IIN IOLD IOHD Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) 5.5 5.5 50 −50 mA mA VOLD = 1.65V Max VOHD = 3.85V Min 5.5 0.50 0.50 0.50 V µA IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND V V IOH = −12 mA IOH = −24 mA IOH = −24 mA IOUT = 50 µA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions ±1.0 3 www.national.com DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) ICC Maximum Quiescent Supply Current Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. (Continued) 54AC TA = −55˚C to +125˚C Guaranteed Limits 80.0 Units Conditions 5.5 µA VIN = VCC or GND Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 (Note 5) VIN = VIL or VIH 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. Units Conditions V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA V V IOH = −24 mA IOH = −24 mA IOUT = 50 µA 0.50 0.50 V µA mA mA mA µA IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND 5.5 5.5 5.5 5.5 5.5 ±1.0 1.6 50 −50 80.0 www.national.com 4 AC Electrical Characteristics VCC Symbol Parameter (V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 54AC TA = −55˚C to +125˚C CL = 50 pF Min fmax tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn Note 8: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V Units Fig. No. Max MHz 14.0 10.5 13.0 10.0 13.5 11.0 ns ns ns 65 90 1.0 1.5 1.0 1.5 1.0 1.5 AC Operating Requirements VCC Symbol Parameter (V) (Note 9) ts th tw tw trec Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP MR Pulse Width, LOW CP Pulse Width Recovery Time MR to CP Note 9: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V 54AC TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum 7.5 5.5 3.0 3.0 7.0 5.0 7.0 5.0 3.0 2.0 ns ns ns ns Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 ns AC Electrical Characteristics Symbol Parameter VCC (V) (Note 10) 5.0 5.0 5.0 5.0 54ACT TA = −55˚C to +125˚C CL = 50 pF Min fmax tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn Note 10: Voltage Range 5.0 is 5.0V ±0.5V Units Fig. No. Max MHz 12.5 13.0 12.0 ns ns ns 95 1.5 1.5 1.5 5 www.national.com AC Operating Requirements VCC Symbol Parameter (V) (Note 11) 54ACT TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum ts th tw tw trec Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP MR Pulse Width, LOW CP Pulse Width, HIGH OR LOW Recovery Time MR to CP Note 11: Voltage Range 5.0 is 5.0V ±0.5V Fig. Units No. 5.0 5.0 5.0 5.0 5.0 3.0 2.0 5.0 5.0 1.0 ns ns ns ns ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 85.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 www.national.com 54AC174 • 54ACT174 Hex D Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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