4-Stage Synchronous Bidirectional Counter

www.DataSheet4U.com 54AC169 • 54ACT169 4-Stage Synchronous Bidirectional Counter July 1998 54AC169 • 54ACT169 4-Stage Synchronous Bidirectional Counter General Description The ’AC/’ACT169 is fully synchronous 4-stage up/down counter. The ’AC/’ACT169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock. n n n n n n Synchronous counting and loading Built-In lookahead carry capability Presettable for programmable operation Outputs source/sink 24 mA ’ACT has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 5962-91603 Features n ICC reduced by 50% Logic Symbols Pin Names CEP CET CP P0–P3 PE U/D DS100276-1 Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Parallel Data Inputs Parallel Enable Input Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output Q0–Q3 TC IEEE/IEC DS100276-2 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100276 www.national.com Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100276-3 DS100276-4 Logic Diagram DS100276-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Functional Description The ’AC/’ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0–P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state occurs, the ’AC169 will return to the legitimate sequence within two counts. Since 2 www.national.com Functional Description (Continued) State Diagrams the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1. Count Enable = CEP •CET • PE 2. Up: TC = Q0 •Q1 •Q 2Q3 •(Up)•CET 3. Down: TC = Q0 • Q1 •Q2 •Q3 •(Down)•CET Mode Select Table DS100276-6 PE L H H H H CEP X L L H X CET X L L X H U/D X H L X X Action on Rising Clock Edge Load (Pn to Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 3 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns ±50 mA ±50 mA −65˚C to +150˚C 175˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) 54AC TA = −55˚C to +125˚C Guaranteed Limits VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 IIN Maximum Input Leakage Current 5.5 0.50 0.50 0.50 V µA IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND V V IOH = −12 mA IOH = −24 mA IOH = −24 mA IOUT = 50 µA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions ±1.0 www.national.com 4 DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) (Continued) 54AC TA = Units Conditions −55˚C to +125˚C Guaranteed Limits IOLD IOHD ICC Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 50 −50 80.0 mA mA µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC (V) 54ACT TA = −55˚C to +125˚C Guaranteed Limits VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 (Note 5) VIN = VIL or VIH 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. Units Conditions V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA V V IOH = −24 mA IOH = −24 mA IOUT = 50 µA 0.50 0.50 V µA mA mA mA µA IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND 5.5 5.5 5.5 5.5 5.5 ±1.0 1.6 50 −50 80.0 5 www.national.com AC Electrical Characteristics VCC Symbol Parameter (V) (Note 8) Min fmax tPLH Maximum Clock Frequency Propagation Delay CP to Qn (PE HIGH or LOW) tPHL Propagation Delay CP to Qn (PE HIGH or LOW) tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC Propagation Delay U/D to TC Propagation Delay U/D to TC Note 8: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V 54AC TA = −55˚C to +125˚C CL = 50 pF Max MHz 15.0 12.0 16.5 13.0 22.0 16.0 22.0 16.0 18.5 13.0 16.0 11.0 18.5 13.0 16.5 12.0 ns ns ns ns ns ns ns ns 55 75 1.0 1.5 1.0 1.5 3.0 3.0 3.0 3.0 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 AC Operating Requirements VCC Symbol Parameter (V) (Note 9) 54AC TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP th ts Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW CEP to CP th ts Hold Time, HIGH or LOW CEP to CP Setup Time, HIGH or LOW CET to CP 3.3 5.0 3.3 5.0 0.5 2.5 13.5 9.0 ns ns 3.3 5.0 3.3 5.0 2.0 2.5 13.5 9.0 ns ns 3.3 5.0 7.0 4.5 ns Units Fig. No. www.national.com 6 AC Operating Requirements (Continued) 54AC TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum Units VCC Symbol Parameter (V) (Note 9) Fig. No. th ts Hold Time, HIGH or LOW CET to CP Setup Time, HIGH or LOW PE to CP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 0.5 2.5 8.5 6.5 0.5 2.0 13.0 9.0 0.5 2.0 5.0 5.0 ns ns ns th ts Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW U/D to CP ns ns ns th tw Hold Time, HIGH or LOW U/D to CP CP Pulse Width, HIGH or LOW Note 9: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V AC Electrical Characteristics VCC Symbol Parameter (V) (Note 10) Min fmax tPLH Maximum Clock Frequency Propagation Delay CP to Qn (PE HIGH or LOW) tPHL Propagation Delay CP to Qn (PE HIGH or LOW) tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC Propagation Delay U/D to TC Propagation Delay U/D to TC 5.0 1.5 14.5 ns 5.0 1.5 14.5 ns 5.0 1.5 13.5 ns 5.0 1.5 13.5 ns 5.0 1.5 16.5 ns 5.0 1.5 16.5 ns 5.0 1.5 12.5 ns 5.0 1.5 12.5 ns 5.0 75 54ACT TA = −55˚C to +125˚C CL = 50 pF Max MHz Units Fig. No. 7 www.national.com AC Electrical Characteristics Note 10: Voltage Range 5.0 is 5.0V ±0.5V (Continued) AC Operating Requirements VCC Symbol Parameter (V) (Note 11) 54ACT TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP th ts Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW CEP to CP t