16-BIT BUS TRANSCEIVERS AND REGISTERS

www.DataSheet4U.com 54AC16652, 74AC16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS242A – MARCH 1990 – REVISED APRIL 1996 D D D D D D D D Members of the Texas Instruments Widebus ™ Family Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings 54AC16652 . . . WD PACKAGE 74AC16652 . . . DL PACKAGE (TOP VIEW) description The ’AC16652 are 16-bit bus transceivers that consist of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. They can be used as two 8-bit transceivers or one 16-bit transceiver. Complementary output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’AC16652. 1OEAB 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2OEAB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OEBA 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OEBA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Copyright © 1996, Texas Instruments Incorporated • DALLAS, TEXAS 75265 1 54AC16652, 74AC16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS242A – MARCH 1990 – REVISED APRIL 1996 description (continued) Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. The 74AC16652 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16652 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC16652 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CLKAB L ↑ ↑ ↑ L ↑ X X X L L CLKBA L ↑ L ↑ ↑ ↑ X L X X L SAB X X X X‡ X X X X L H H SBA X X X X X X‡ L H X X H A1–A8 Input Input Input Input Unspecified‡ Output Output Output Input Input Output DATA I/O† B1–B8 Input Input Unspecified‡ Output Input Input Input Input Output Output Output OPERATION OR FUNCTION Isolation Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers Real-time B data to A bus Stored B data to A bus Real-time A data to B bus Stored A data to B bus Stored A data to B bus and stored B data to A bus † The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load both registers. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC16652, 74AC16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS242A – MARCH 1990 – REVISED APRIL 1996 BUS B OEAB OEBA L L CLKAB CLKBA SAB X X X SBA L OEAB OEBA H H CLKAB X CLKBA X SAB L BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB L CLKBA L SAB H BUS B SBA H TRANSFER STORED DATA TO A AND/OR B BUS A REAL-TIME TRANSFER BUS B TO BUS A BUS B BUS A OEAB X L L OEBA H X H CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ X X X SBA X X X OEAB H OEBA L STORAGE FROM A, B, OR A AND B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 BUS A BUS A 3 54AC16652, 74AC16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS242A – MARCH 1990 – REVISED APRIL 1996 logic symbol† 56 1OEBA 1OEAB 1CLKBA 1SBA 1CLKAB 1SAB 2OEBA 2OEAB 2CLKBA 2SBA 2CLKAB 2SAB 1 55 54 2 3 29 28 30 31 27 26 EN1 [BA] EN2 [AB] C3 G4 C5 G6 EN7 [BA] EN8 [AB] C9 G10 C11 G12 ≥1 1 5D 6 8 9 10 12 13 14 15 7 11D 12 16 17 19 20 21 23 24 1 12 ≥1 10 ≥1 8 2A2 2A3 2A4 2A5 2A6 2A7 2A8 41 40 38 37 36 34 33 2B2 2B3 2B4 2B5 2B6 2B7 2B8 9D 1 6 6 4 41 ≥1 2 51 49 48 47 45 44 43 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 3D 52 1B1 1A1 5 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 10 1 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC16652, 74AC16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS242A – MARCH 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1OEBA 1OEAB 1CLKBA 1SBA 56 1 55 54 1CLKAB 2 3 1SAB C1 TG 1A1 5 TG C1 1D 52 TG 1B1 TG 1D To Seven Other Channels 2OEBA 2OEAB 2CLKBA 2SBA 29 28 30 31 2CLKAB 27 26 2SAB C1 TG 2A1 15 TG C1 1D 42 TG 2B1 TG 1D To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 54AC16652, 74AC16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS242A – MARCH 1990 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_ C and a board trace length of 750 mils. recommended operating conditions (see Note 3) 54AC16652 MIN VCC VIH Supply voltage (see Note 4) High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL ∆t/∆v Low-level output current Input transition rise or fall rate VCC = 4.5 V VCC = 5.5 V 0 VCC = 4.5 V VCC = 5.5 V 0 0 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –4 –24 –24 12 24 24 10 125 0 –40 0 0 NOM 5 MAX 5.5 74AC16652 MIN 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –4 –24 –24 12 24 24 10 85 ns/V °C mA mA V V V V NOM 5 MAX 5.5 UNIT V TA Operating free-air temperature –55 NOTES: 3. Unused inputs must be held high or low to prevent them from floating. 4. All VCC and GND pins must be connected to the proper voltage power supply. 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