16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

www.DataSheet4U.com 54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 D D D D D D D D Members of the Texas Instruments Widebus ™ Family 3-State True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings 54AC16374 . . . WD PACKAGE 74AC16374 . . . DL PACKAGE (TOP VIEW) description The ’AC16374 are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK The ’AC16374 can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74AC16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16374 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC16374 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Copyright © 1996, Texas Instruments Incorporated • DALLAS, TEXAS 75265 1 54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 FUNCTION TABLE INPUTS OE L L L L H CLK ↑ ↑ X ↓ X D H L X X X OUTPUT Q H L Q0 Q0 Z logic symbol† 1OE 1CLK 2OE 2CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2D 2 1EN C1 2EN C2 1D 2 1 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1OE 1CLK 1 48 C1 1D1 47 1D 2OE 2CLK 2 24 25 C1 1Q1 2D1 36 1D 13 2Q1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power package dissipation at TA = 55°C (in still air)(see Note 2): DL package . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 recommended operating conditions (see Note 3) 54AC16374 MIN VCC VIH Supply voltage High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL ∆t/∆v Low-level output current Input transition rise or fall rate VCC = 4.5 V VCC = 5.5 V 0 –55 VCC = 4.5 V VCC = 5.5 V 0 0 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –4 –24 –24 12 24 24 10 125 0 –40 0 0 NOM 5 MAX 5.5 74AC16374 MIN 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –4 –24 –24 12 24 24 10 85 ns/V °C mA mA V V V V NOM 5 MAX 5.5 UNIT V TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 3V IOH = –50 µA VOH IOH = –4 mA IOL = –24 mA 24 A IOH = –75 mA† IOL = 50 µA VOL IOL = 12 mA IOL = 24 mA IOL = 75 mA† VI = VCC or GND VO = VCC or GND VI = VCC or GND, VI = VCC or GND VO = VCC or GND IO = 0 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 5V 3 11 ±0.1 ±0.5 8 0.1 0.1 0.1 0.36 0.36 0.36 MIN 2.9 4.4 5.4 2.58 3.94 4.94 TA = 25°C TYP MAX 54AC16374 MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 ±1 ±5 80 MAX 74AC16374 MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 ±1 ±5 80 µA µA µA pF pF V V MAX UNIT II IOZ ICC Ci Co † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 timing requirements over recommended operating free-air temperature range VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time, data before CLK↑ Hold time, data after CLK↑ CLK high or low 0 8.3 7.5 0 60 54AC16374 MIN 0 8.3 7.5 0 MAX 60 74AC16374 MIN 0 8.3 7.5 0 MAX 60 UNIT MHz ns ns ns timing requirements over recommended operating free-air temperature range VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time, data before CLK↑ Hold time, data after CLK↑ CLK high or low 0 5 5 0 100 54AC16374 MIN 0 5 5 0 MAX 100 74AC16374 MIN 0 5 5 0 MAX 100 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 60 CLK Q Q Q 4.9 4.8 4.3 5.3 4 3.8 12.2 11.9 11.9 15.5 7.3 7.1 15 14.3 14.7 18.7 9 8.8 54AC16374 MIN 60 4.9 4.8 4.3 5.3 4 3.8 17 15.7 16.8 21.2 9.8 9.4 MAX 74AC16374 MIN 60 4.9 4.8 4.3 5.3 4 3.8 17 15.7 16.8 21.2 9.8 9.4 MAX UNIT MHz ns ns ns OE OE switching characteristics over recommended operating free-air temperature range VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 100 CLK Q Q Q 3.8 3.8 3.2 3.8 3.7 3.5 7.6 7.6 7.2 8.7 6 5.8 9.5 9.5 9 10.7 7.5 7.3 54AC16374 MIN 100 3.8 3.8 3.2 3.8 3.7 3.5 10.8 10.6 10.2 12.1 8.2 7.9 MAX 74AC16374 MIN 100 3.8 3.8 3.2 3.8 3.7 3.5 10.8