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Part Number |
54ACT138 |
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Manufacturer |
National Semiconductor |
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Semiconductor DataSheet |
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DataSheet View |
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54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer
August 1998
54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer
General Description
The ’AC/’ACT138 is a high-speed 1-of-8 decoder/ demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three ’AC/’ACT138 devices or a 1-of-32 decoder using four ’AC/’ACT138 devices and one inverter.
Features
n n n n n n n ICC reduced by 50% Demultiplexing capability Multiple input enable for easy expansion Active LOW mutually exclusive outputs Outputs source/sink 24 mA ’ACT138 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC138: 5962-87622 — ’ACT138: 5962-87554
Logic Symbols
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100268-1
IEEE/IEC
DS100268-2
Pin Assignment for LCC
DS100268-7
Pin Names A0–A2 E1–E2 E3 O0–O7
Description Address Inputs Enable Inputs Enable Input Outputs
DS100268-3
FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100268
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Functional Description
The ’AC/’ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0–O7). The ’AC/’ACT138 features three Enable inputs, two active-LOW (E1, E2) and one active-HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four ’AC/’ACT138 devices and one inverter (see Figure 1). The ’AC/’ACT138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active-HIGH or active-LOW state.
Truth Table
Inputs E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H Outputs O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
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Logic Diagram
DS100268-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Logic Diagram
(Continued)
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DS100268-5
FIGURE 1. Expansion to 1-of-32 Decoding
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V
Recommended Operating Conditions
Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C
± 50 mA ± 50 mA −65˚C to +150˚C
175˚C
125 mV/ns
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
Symbol Parameter VCC (V) VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 3.0 4.5 5.5 VIL 3.0 4.5 5.5 VOH 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD Maximum Input Leakage Current (Note 3) Minimum Dynamic Output Current 5.5 5.5 50 −50 mA mA VOLD = 1.65V Max VOHD = 3.85V Min 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH 0.50 0.50 0.50 V µA 12 mA IOL 24 mA 24 mA VI = VCC, GND V IOUT = 50 µA V IOH −12 mA −24 mA −24 mA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions
± 1.0
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DC Characteristics for ’AC Family Devices
Symbol Parameter VCC (V) ICC Maximum Quiescent Supply Current 54AC TA =
(Continued)
Units
Conditions
−55˚C to +125˚C Guaranteed Limits VIN = VCC or GND
5.5
80.0
µA
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input (Note 6) Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 50 −50 mA mA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND 5.5 80.0 µA 5.5 1.6 mA VI = VCC − 2.1V 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH 3.70 4.70 0.1 0.1 (Note 5) VIN = VIL or VIH 0.50 0.50 V µA VI = VCC, GND IOL 24 mA 24 mA V IOUT = 50 µA V IOH −24 mA −24 mA V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA Units Conditions
± 1.0
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
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AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 8) Min tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay An to On Propagation Delay An to On Propagation Delay E1 or E2 to On Propagation Delay E1 or E2 to On Propagation Delay E3 to On Propagation Delay E3 to On
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V
54AC TA = −55˚C to +125˚C CL = 50 pF Max 16.0 12.0 15.0 11.5 16.5 13.0 15.5 12.0 17.0 13.5 15.0 11.0 ns ns ns ns ns ns 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 Units
Fig. No.
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 9) Min tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay An to On Propagation Delay An to On Propagation Delay E1 or E2 to On Propagation Delay E1 or E2 to On Propagation Delay E3 to O n Propagation Delay E3 to O n
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
54ACT TA = −55˚C to +125˚C CL = 50 pF Max 12.5 12.5 13.5 12.5 14.0 12.0 ns ns ns ns ns ns 1.5 1.5 1.5 1.5 1.5 1.5 Units
Fig. No.
5.0 5.0 5.0 5.0 5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 60.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V
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Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A
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54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16 Lead Ceramic Flatpak (F) NS Package Number W16A
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