OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

www.DataSheet4U.com 54AC11534, 74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS037A – JULY 1987 – REVISED APRIL 1993 • • • • • • • • • Eight D-Type Flip-Flops in a Single Package 3-State Bus Driving Inverting Outputs Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-m m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 54AC11534 . . . JT PACKAGE 74AC11534 . . . DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OC 1D 2D 3D 4D VCC VCC 5D 6D 7D 8D CLK 54AC11534 . . . FK PACKAGE (TOP VIEW) description These eight flip-flops feature 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ′AC11534 are edgetriggered, D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the complement of the logic levels at the D inputs. The ′AC11534 is functionally equivalent to the ′AC11374 except for having inverted outputs. An output-control input (OC) is used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output control (OC) does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 54AC11534 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11534 is characterized for operation from – 40°C to 85°C. 3D 4D VCC NC VCC 5D 6D 2D 1D OC NC 1Q 2Q 3Q 5 6 7 8 9 10 4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18 7D 8D CLK NC 8Q 7Q 6Q NC – No internal connection OC L L L H 4Q GND GND NC GND GND 5Q FUNCTION TABLE (each filp-flop) INPUTS CLK ↑ ↑ L X D H L X X OUTPUT Q L H Q0 Z Copyright © 1993, Texas Instruments Incorporated EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 54AC11534, 74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS037A – JULY 1987 – REVISED APRIL 1993 logic symbol† OC CLK 1D 2D 3D 4D 5D 6D 7D 8D 24 13 23 22 21 20 17 16 15 14 EN C1 1D 1 2 3 4 9 10 11 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q logic diagram (positive logic) OC CLK 24 13 C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D 12 11 10 9 4 3 2 1 1D 23 1Q 2D 22 2Q 3D 21 3Q 4D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 5D 20 4Q 17 5Q 6D 16 6Q 7D 15 7Q 8D Pin numbers shown are for the DW, JT, and NT packages. 14 8Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC11534, 74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS037A – JULY 1987 – REVISED APRIL 1993 recommended operating conditions 54AC11534 MIN VCC VIH Supply voltage High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL Low-level output current VCC = 4.5 V VCC = 5.5 V OC D 0 0 – 55 VCC = 4.5 V VCC = 5.5 V 0 0 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –4 – 24 – 24 12 24 24 5 10 125 0 0 – 40 0 0 NOM 5 MAX 5.5 74AC11534 MIN 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –4 – 24 – 24 12 24 24 5 10 85 ns/ V °C mA mA V V V V NOM 5 MAX 5.5 UNIT V D t /D v TA Input transition rise or fall rate Operating free-air temperature electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 3V IOH = – 50 m A IOH = – 4 mA IOH = – 24 mA IOH IOH = – 75 mA{ IOL = 50 m A IOL = 12 mA IOL = 24 mA IOL = 50 mA{ IOL = 75 mA{ IOZ II ICC Ci Co VO = VCC or GND VI = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 = – 50 mA{ 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V VOL 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4 ± 0.5 ± 0.1 8 ± 10 ±1 160 0.1 0.1 0.1 0.36 0.36 0.36 0.1 0.1 0.1 0.5 0.5 0.5 1.65 1.65 ±5 ±1 80 VOH MIN 2.9 4.4 5.4 2.58 3.94 4.94 TA = 25°C TYP MAX 54AC11534 MIN 2.9 4.4 5.4 2.4 3.7 4.7 3.85 3.85 0.1 0.1 0.1 0.44 0.44 0.44 V MAX 74AC11534 MIN 2.9 4.4 5.4 2.48 3.8 4.8 V MAX UNIT mA mA mA pF pF VO = VCC or GND 5V 10 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 54AC11534, 74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS037A – JULY 1987 – REVISED APRIL 1993 timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1) TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration, CLK low or CLK high Setup time, data before CLK ↑ Hold time, data after CLK ↑ 0 10 3.5 5.5 50 54AC11534 MIN 0 10 3.5 5.5 MAX 50 74AC11534 MIN 0 10 3.5 5.5 MAX 50 UNIT MHz ns ns ns timing requirements, VCC = 5 V ± 0.5 V (see Figure 1) TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration, CLK low or CLK high Setup time, data before CLK ↑ Hold time, data after CLK ↑ 0 6.5 3.5 4.5 75 54AC11534 MIN 0 6.5 3.5 4.5 MAX 75 74AC11534 MIN 0 6.5 3.5 4.5 MAX 75 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 50 CLK 1.5 Q Q Q 1.5 1.5 OC OC 1.5 1.5 1.5 TA = 25°C TYP MAX 75 11 11 9 9 10 8 15.3 15.7 12.8 12.6 12.6 13 54AC11534 MIN 50 1.5 1.5 1.5 1.5 1.5 1.5 19.1 19 15.8 15.6 13.8 14.2 MAX 74AC11534 MIN 50 1.5 1.5 1.5 1.5 1.5 1.5 17.6 17.7 14.6 14.3 13.3 13.8 MAX UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 75 CLK 1.5 Q Q Q 1.5 1.5 OC OC 1.5 1.5 1.5 TA = 25°C TYP MAX 100 7 7 6 6 9 6 10.3 10.7 9.2 9.2 11.1 8.8 54AC11534 MIN 75 1.5 1.5 1.5 1.5 1.5 1.5 12.7 13.2 11.2 11.3 11.9 9.6 MAX 74AC11534 MIN 75 1.5 1.5 1.5 1.5 1.5 1.5 11.7 12.1 10.4 10.4 11.6 9.2 MAX UNIT MHz ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per flip flop flip-flop Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 75 65 UNIT pF 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54AC11534, 74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS037A – JULY 1987 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION 2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 Ω S1 Open GND 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND LOAD CIRCUIT Timing Input (see Note B) tw VCC Input 50% 50% 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input tsu 50% 50% th VCC 50% 0V VCC 0V Input (see Note B) tPLH In-Phase Output tPHL Out-of-Phase Output VCC 50% 50% 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C) VCC 50% tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 50% 0V [ VCC VOL tPZH 50% VCC [ 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and ji