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www.DataSheet4U.com TECHNICAL MANUAL LSI53CF92A Fast SCSI Controller April 2002 Version 2.1 ® www.DataSheet4U.com This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000094-02, Third Edition (April 2002) This document describes the LSI Logic LSI53CF92A Fast SCSI Controller and will remain the official reference source for all revisions of this product until rescinded by an update. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design, SCRIPTS, SYM, and TolerANT are trademarks or registered trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. AP To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales offices, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesoffices.html ii Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. www.DataSheet4U.com Preface This book is the primary reference and technical manual for the LSI53CF92A Fast SCSI Controller. It contains a complete functional description and includes complete physical and electrical specifications. Audience This document assumes that you have some familiarity with current and proposed SCSI standards. The people who benefit from this book are: • • Organization Engineers and managers who are evaluating the controller for possible use in a system Engineers who are designing the controller into a system This document has the following chapters and appendixes: • • • • • • • • Chapter 1, Introduction Chapter 2, Functional Description Chapter 3, Signal Descriptions Chapter 4, Registers Chapter 5, Command Set Chapter 6, Electrical Specifications Appendix A, Register Map Appendix B, Wiring Diagram LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. iii www.DataSheet4U.com Related Publications ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Document No. X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740 ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 SCSI: Understanding the Small Computer System Interface, ISBN 0-13-796855-8 LSI Logic World Wide Web Home Page www.lsil.com SCSI SCRIPTS™ Processors Programming Guide, Order No. S14044.A SCAM specification X3T9.2/93-109r5 PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 iv Preface Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. www.DataSheet4U.com Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111. Revision Record Revision 1.0 1.1 2.0 2.1 Date 12/97 4/99 11/00 12/01 Remarks First version. Miscellaneous edits, reformat. All product names changed from SYM® to LSI. Updated Tables 6.7, 6.13, and 6.15 and Figures 6.9, 6.12, and 6.16. Preface Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. v www.DataSheet4U.com vi Preface Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. www.DataSheet4U.com Contents Chapter 1 Introduction 1.1 General Description 1.2 SCSI-Configured AutoMatically (SCAM) Capability 1.3 TolerANT® Technology 1.4 Features Functional Description 2.1 Typical SCSI Operation 2.2 Bus-Initiated Sequences 2.2.1 Bus-Initiated Selection 2.2.2 Bus-Initiated Reselection 2.2.3 Bus-Initiated Reset 2.2.4 Stacked Commands 2.3 Parity Checking and Generation 2.4 Host Bus Configuration 2.4.1 Mode Description 2.4.2 Multiplexed Bus Configuration Mode 2.4.3 Nonmultiplexed Bus Configuration Mode 2.5 DMA Operation 2.5.1 DMA Threshold 2.5.2 Normal DMA Mode 2.5.3 Threshold Eight Mode 2.5.4 DMA Burst Mode 2.5.5 Single-Pin, SE SCSI 2.6 SCSI Data Transfer Rates 2.6.1 Asynchronous Operation 2.6.2 Synchronous Operation 2.7 Chip Reset 1-1 1-2 1-2 1-3 Chapter 2 2-2 2-3 2-4 2-5 2-6 2-6 2-6 2-8 2-8 2-8 2-9 2-9 2-9 2-9 2-10 2-11 2-13 2-14 2-14 2-14 2-15 LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. vii www.DataSheet4U.com 2.8 2.7.1 Hard Reset 2.7.2 Soft Reset 2.7.3 Disconnect Reset SCAM Capabilities 2.8.1 SCSI Low-Level Programming 2.8.2 SCAM Operations 2-15 2-16 2-17 2-17 2-18 2-18 Chapter 3 Chapter 4 Signal Descriptions Registers 4.1 Standard Register Set 4.2 SCAM Register Set Command Set 5.1 Illegal Commands 5.1.1 Stacked Commands 5.2 Miscellaneous Command Group 5.2.1 No-Operation (NOP) 5.2.2 Flush FIFO 5.2.3 Reset Chip 5.2.4 Reset SCSI Bus 5.2.5 Disable Selection/Reselection 5.3 Disconnected State Command Group 5.3.1 Reselect Sequence 5.3.2 Select without ATN Sequence 5.3.3 Select with ATN Sequence 5.3.4 Select with ATN and Stop Sequence 5.3.5 Enable Selection/Reselection 5.3.6 Select with ATN3 Sequence 5.3.7 Reselect3 Sequence 5.4 Initiator Command Group 5.4.1 Transfer Information 5.4.2 Initiator Command Complete Sequence 5.4.3 Message Accepted 5.4.4 Transfer Pad 5.4.5 Set ATN 5.4.6 Reset ATN 5.4.7 Set ATN Immediate 4-4 4-36 Chapter 5 5-3 5-3 5-4 5-4 5-4 5-4 5-5 5-5 5-5 5-6 5-6 5-7 5-7 5-11 5-11 5-12 5-12 5-14 5-15 5-15 5-16 5-16 5-16 5-17 viii Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. www.DataSheet4U.com 5.5 Target Command Group 5.5.1 Send Message 5.5.2 Send Status 5.5.3 Send Data 5.5.4 Disconnect Sequence 5.5.5 Terminate Sequence 5.5.6 Target Command Complete Sequence 5.5.7 Disconnect 5.5.8 Receive Message 5.5.9 Receive Command 5.5.10 Receive Data 5.5.11 Receive Command Sequence 5.5.12 Target Abort DMA 5-17 5-18 5-18 5-18 5-19 5-19 5-20 5-20 5-21 5-21 5-21 5-21 5-22 Chapter 6 Electrical Specifications 6.1 DC Electrical Characteristics 6.2 TolerANT Active Negation Technology Specifications 6.3 AC Electrical Characteristics 6.3.1 Register Interface, Nonmultiplexed PAD Bus 6.3.2 Register Interface, Multiplexed PAD Bus 6.3.3 DMA Interface (Nonmultiplexed Mode Only) 6.3.4 DMA Interface (Multiplexed Mode Only) 6.3.5 Burst Mode DMA Interface (Multiplexed Mode) 6.3.6 Burst Mode DMA Interface (Nonmultiplexed Mode) 6.4 SCSI Timing Diagrams 6.5 Package Drawings Register Map Wiring Diagram Index Customer Feedback 6-1 6-4 6-7 6-11 6-13 6-15 6-17 6-19 6-21 6-23 6-29 Appendix A Appendix B Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ix www.DataSheet4U.com x Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. www.DataSheet4U.com Figures 1.1 1.2 Functional Block Diagram Bus Configuration, Multiplexed Mode (Dual Bus, 8-Bit DMA Bus and 8-Bit Multiplexed Processor Address/Data Bus) Bus Configuration, Nonmultiplexed Mode (Dual Bus, 8-Bit DMA Bus and 8-Bit Processor Bus) Normal DMA Mode DMA Burst Mode (Multiplexed Mode and Nonmultiplexed Mode Writes) DMA Burst Mode (Nonmultiplexed Mode Reads) SCAM Transfer Cycles Functional Signal Grouping LSI53CF92A 64-Pin Plastic QFP and Thin QFP Pin Configuration1 REQ/ ACK/ Deassertion Delay Rise and Fall Time Test Conditions SCSI Input Filtering Hysteresis of SCSI Receivers Input Current as a Function of Input Voltage Output Current as a Function of Output Voltage Clock Input Reset Input Interrupt Output Register Read, Nonmultiplexed PAD Bus Register Write, Nonmultiplexed PAD Bus Register Read, Multiplexed PAD Bus Register Write, Multiplexed PAD Bus DMA Read, Nonmultiplexed Mode Only DMA Write, Nonmultiplexed Mode Only DMA Read, Multiplexed Mode Only DMA Write, Multiplexed Mode Only Burst Mode DMA Read, Multiplexed Mode Only Burst Mode DMA Write, Multiplexed Mode Only Burst Mode DMA Read, Nonmultiplexed Mode Only Burst Mode DMA Write, Nonmultiplexed Mode Only Initiator Asynchronous Send 1-4 1-5 1-5 2-10 2-13 2-13 2-23 3-1 3-6 4-23 6-5 6-5 6-5 6-6 6-6 6-8 6-9 6-10 6-11 6-11 6-13 6-13 6-15 6-15 6-17 6-17 6-19 6-19 6-21 6-21 6-23 1.3 2.1 2.2 2.3 2.4 3.1 3.2 4.1 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. xi www.DataSheet4U.com 6.22 6.23 6.24 6.25 6.26 6.27 6.28 B.1 Initiator Asynchronous Receive Target Asynchronous Send Target Asynchronous Receive Target and Initiator Synchronous Output Target and Initiator Synchronous Input 64-Pin Plastic Quad Flat Pack 64-Pin Thin Quad Flat Pack Single-Pin, SE SCSI Bus Interface Wiring Diagram 6-24 6-25 6-26 6-27 6-27 6-29 6-30 B-1 xii Contents Copyright © 1995–2002 by