Search -----> HM5264165FTT75

www.DataSheet4U.com HM5264165F-75/A60/B60 HM5264805F-75/A60/B60 HM5264405F-75/A60/B60 64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-940B (Z) Rev. 1.0 Nov. 10, 1999 Description The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi HM5264405F is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II. Features • • • • • • • • 3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence  Sequential (BL = 1/2/4/8/full page)  Interleave (BL = 1/2/4/8) HM5264165F/HM5264805F/HM5264405F-75/A60/B60 www.DataSheet4U.com • Programmable CAS latency: 2/3 • Byte control by DQM: DQM (HM5264805F/HM5264405F) DQMU/DQML (HM5264165F) • Refresh cycles: 4096 refresh cycles/64 ms • 2 variations of refresh  Auto refresh  Self refresh • Full page burst length capability  Sequential burst  Burst stop capability Ordering Information Type No. HM5264165FTT-75* HM5264165FTT-A60 HM5264165FTT-B60 *2 HM5264165FLTT-75 *1 HM5264165FLTT-A60 HM5264165FLTT-B60 *2 HM5264805FTT-75 *1 HM5264805FTT-A60 HM5264805FTT-B60 *2 HM5264805FLTT-75 *1 HM5264805FLTT-A60 HM5264805FLTT-B60 *2 HM5264405FTT-75 *1 HM5264405FTT-A60 HM5264405FTT-B60 *2 HM5264405FLTT-75 *1 HM5264405FLTT-A60 HM5264405FLTT-B60 *2 Note: 1 Frequency 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz CAS latency 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 Package 400-mil 54-pin plastic TSOP II (TTP-54D) 1. 100 MHz operation at CAS latency = 2. 2. 66 MHz operation at CAS latency = 2. 2 www.DataSheet4U.com HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264165F) 54-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A13 Function Address input  Row address  Column address A0 to A11 A0 to A7 Pin name WE Function Write enable DQMU/DQML Input/output mask CLK Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection  Bank select address A12/A13 (BS) CKE DQ0 to DQ15 CS RAS CAS Data-input/output Chip select Row address strobe command Column address strobe command VCC VSS VCCQ VSS Q NC 3 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 www.DataSheet4U.com Pin Arrangement (HM5264805F) 54-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A13 Function Address input  Row address  Column address A0 to A11 A0 to A8 Pin name WE DQM CLK Function Write enable Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection  Bank select address A12/A13 (BS) CKE DQ0 to DQ7 CS RAS CAS Data-input/output Chip select Row address strobe command Column address strobe command VCC VSS VCCQ VSS Q NC 4 www.DataSheet4U.com HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264405F) 54-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A13 Function Address input  Row address  Column address A0 to A11 A0 to A9 Pin name WE DQM CLK Function Write enable Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection  Bank select address A12/A13 (BS) CKE DQ0 to DQ3 CS RAS CAS Data-input/output Chip select Row address strobe command Column address strobe command VCC VSS VCCQ VSS Q NC 5 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 www.DataSheet4U.com Block Diagram (HM5264165F) A0 to A13 A0 to A7 A0 to A13 Column address counter Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder Row decoder Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Column decoder Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Memory array Column decoder Bank 0 Bank 1 Bank 2 Bank 3 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit Input buffer Output buffer Control logic & timing generator DQ0 to DQ15 DQMU /DQML CLK CKE RAS CAS WE CS 6 www.DataSheet4U.com HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264805F) A0 to A13 A0 to A8 A0 to A13 Column address counter Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder Row decoder Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Column decoder Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Memory array Bank 3 Column decoder Bank 0 Bank 1 Bank 2 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit Input buffer Output buffer Control logic & timing generator DQ0 to DQ7 DQM CLK CKE RAS CAS WE CS 7 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 www.DataSheet4U.com Block Diagram (HM5264405F) A0 to A13 A0 to A9 A0 to A13 Column address counter Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder Row decoder Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Column decoder Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Memory array Column decoder Bank 0 Bank 1 Bank 2 Bank 3 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit Input buffer Output buffer Control logic & timing generator DQ0 to DQ3 DQM CLK CKE RAS CAS WE CS 8 www.DataSheet4U.com HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) is determined by A0 to A7, A8 or A9 (A7; HM5264165F, A8; HM5264805F, A9; HM5264405F) level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BS) is precharged. For details refer to the command operation section. A12/A13 (input pins): A12/A13 are bank select signal (BS). The memory array of the HM5264165F, HM5264805F, the HM5264405F is divided into bank 0, bank 1, bank 2 and bank 3. HM5264165F contain 4096-row × 256-column × 16-bit. HM5264805F contain 4096-row × 512-column × 8-bit. HM5264405F contain 4096-row × 1024-column × 4-bit. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers. Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during reading is 2 clocks.) Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0 clock.) DQ0 to D