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Micron Technology
Micron Technology

46V16M16 Datasheet

Search -----> MT46V16M16


46V16M16 Datasheet Preview


DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• 167 MHz Clock, 333 Mb/s/p data rate
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
tRAS lockout (tRAP = tRCD)
• Backwards compatible with DDR200 and DDR266
OPTIONS
PART NUMBER
www.DatCaSohnefeitg4uU.rcaotmion
64 Meg x 4 (16 Meg x 4 x 4 banks)
64M4
32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8
16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16
• Plastic Package
66-Pin TSOP (OCPL)
TG
60-Ball FBGA (16x9mm)
FJ
• Timing - Cycle Time
6ns @ CL = 2.5 (DDR333B–FBGA)1
6ns @ CL = 2.5 (DDR333B–TSOP)1
7.5ns @ CL = 2 (DDR266A)2
-6
-6T
-75Z
• Self Refresh
Standard
none
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
DDR333 COMPATIBILITY
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and tRAS lockout
for improved timing performance. The 256Mb,
DDR333 device will support an (tREFI) average peri-
odic refresh interval of 7.8us.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
The Micron 256Mb data sheet provides full specifi-
cations and functionality unless specified herein.
CONFIGURATION
Architecture 64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
RefreshCount
8K
8K
8K
RowAddressing
8K (A0–A12)
8K (A0–A12)
8K (A0–A12)
BankAddressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
ColumnAddressing 2K (A0–A9, A11)
1K (A0–A9)
512 (A0– A8)
KEY TIMING PARAMETERS3
SPEED
CLOCK RATE DATA-OUT ACCESS DQS-DQ
GRADE CL = 21 CL = 2.51 WINDOW2 WINDOW SKEW
-6 133 MHz 167 MHz 2.15ns
-6T 133 MHz 167 MHz 2.0ns
±0.70ns +0.35ns
±0.75ns +0.45ns
-75Z 133 MHz 133 MHz 2.5ns ±0.75ns +0.50ns
NOTE:
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. -75, -8 are also available; see base data sheet.
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.
Page 1

PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
FBGA 60-BALL PACKAGE DIMENSION
FBGA PACKAGE PINOUT
0.850 ±0.075
SEATING PLANE
0.10 C
C
61X 0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.40
BALL A9
6.40
1.80
CTR
11.00
5.50 ±0.05
0.80 TYP
PIN A1 ID
BALL A1
8.00 ±0.05
1.20 MAX
CL
1.00
TYP
16.00 ±0.10
Bottom View
CL
3.20 ±0.05
4.50 ±0.05
9 .00 ±0.10
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .33mm
MOLD COMPOUND: EPOXY NOVOLAC
FBGA PACKAGE MARKING
Due to the physical size of the FBGA package, the full
ordering part number is not printed on the package.
Instead the following package code is utilized.
www.TDoatpaSmheaertk4Uc.oconmtains five fields
Field 1 (Product Family)
DRAM
DRAM - ES
Field 2 (Product Type)
2.5 Volt, DDR SDRAM, 60-ball
Field 3 (Width)
x4 devices
x8 devices
x16 devices
Field 4 (Density / Size)
256Mb
Filed 5 (Speed Grade)
-6
-75Z
-75
-8
12345
D
Z
L
B
C
D
H
J
P
F
C
Example top mark for a MT46V32M4FJ-6: DLBFJ
x4 (Top View)
12 3
A VSSQ NC VSS
B NC VDDQ DQ3
C NC VSSQ NC
D NC VDDQ DQ2
E NC VSSQ DQS
F VREF VSS DM
G CK CK#
H A12 CKE
J A11 A9
K A8 A7
L A6 A5
M A4 VSS
45 6
789
A VDD NC VDDQ
B DQ0 VSSQ NC
C NC VDDQ NC
D DQ1 VSSQ NC
E NC VDDQ NC
F NC VDD A13
G WE# CAS#
H RAS# CS#
J BA1 BA0
K A0 A10
L A2 A1
M VDD A3
x8 (Top View)
12 3
A VSSQ DQ7 VSS
B NC VDDQ DQ6
C NC VSSQ DQ5
D NC VDDQ DQ4
E NC VSSQ DQS
F VREF VSS DM
G CK CK#
H A12 CKE
J A11 A9
K A8 A7
L A6 A5
M A4 VSS
45 6
789
A VDD DQ0 VDDQ
B DQ1 VSSQ NC
C DQ2 VDDQ NC
D DQ3 VSSQ NC
E NC VDDQ NC
F NC VDD A13
G WE# CAS#
H RAS# CS#
J BA1 BA0
K A0 A10
L A2 A1
M VDD A3
x16 (Top View)
12 3
A VSSQ DQ15 VSS
B DQ14 VDDQ DQ13
C DQ12 VSSQ DQ11
D DQ10 VDDQ DQ9
E DQ8 VSSQ UDQS
F VREF VSS UDM
G CK CK#
H A12 CKE
J A11 A9
K A8 A7
L A6 A5
M A4 VSS
45 6
789
A VDD DQ0 VDDQ
B DQ2 VSSQ DQ1
C DQ4 VDDQ DQ3
D DQ6 VSSQ DQ5
E LDQS VDDQ DQ7
F LDM VDD A13
G WE# CAS#
H RAS# CS#
J BA1 BA0
K A0 A10
L A2 A1
M VDD A3
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Page 2

66-PIN TSOP PACKAGE DIMENSION
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
66-PIN TSOP PACKAGE PIN ASSIGMENT
22.22 ± 0.08
0.65 TYP
0.32 ± .075 TYP
0.71
0.10 (2X)
SEE DETAIL A
11.76 ±0.10
10.16 ±0.08
PIN #1 ID
+0.03
0.15 -0.02
1.20 MAX
GAGE PLANE
0.25
0.10
0.10
+0.10
-0.05
DETAIL A
0.80 TYP
0.50 ±0.10
(TOP VIEW)
x4 x8 x16
VDD
VDD
VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VssQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VssQ
NC NC DQ7
NC NC NC
VDDQ VDDQ VDDQ
NC NC LDQS
NC NC NC
VDD
VDD
VDD
DNU DNU DNU
NC NC LDM
WE# WE# WE#
CAS# CAS# CAS#
RAS# RAS# RAS#
CS# CS# CS#
NC NC NC
BA0 BA0 BA0
BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
x16 x8 x4
66 VSS
VSS VSS
65 DQ15 DQ7 NC
64 VSSQ VSSQ VSSQ
63 DQ14 NC NC
62 DQ13 DQ6 DQ3
61 VDDQ VDDQ VDDQ
60 DQ12 NC NC
59 DQ11 DQ5 NC
58 VSSQ VSSQ VSSQ
57 DQ10 NC NC
56 DQ9 DQ4 DQ2
55 VDDQ VDDQ VDDQ
54 DQ8 NC NC
53 NC
NC NC
52 VSSQ VSSQ VSSQ
51 UDQS DQS DQS
50 DNU DNU DNU
49
VREF
VREF
VREF
48 VSS
VSS VSS
47 UDM DM DM
46 CK# CK# CK#
45 CK
CK CK
44 CKE CKE CKE
43 NC
NC NC
42 A12 A12 A12
41 A11 A11 A11
40 A9
A9 A9
39 A8
A8 A8
38 A7
A7 A7
37 A6
A6 A6
36 A5
A5 A5
35 A4
A4 A4
34 VSS
VSS VSS
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NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Page 3
Part Number 46V16M16
Manufactur Micron Technology
Description Search -----> MT46V16M16
Total Page 8 Pages
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