Half-bridge Power MOSFET Controller

3946 Half-Bridge Power MOSFET Controller A3946KLB SOIC Data Sheet 29319.150 VREG CP2 CP1 PGND GL S 1 2 3 4 5 6 7 8 16 VBB 15 VREF 14 DT 13 LGND 12 RESET 11 IN2 The A3946 is designed specifically for applications that require high power unidirectional dc motors, three-phase brushless dc motors, or other inductive loads. The A3946 provides two high-current gate drive outputs that are capable of driving a wide range of power N-channel MOSFETs. The high-side gate driver switches an N-channel MOSFET that controls current to the load, while the low-side gate driver switches an N-channel MOSFET as a synchronous rectifier. A bootstrap capacitor provides the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high side allows for dc (100% duty cycle) operation of the half-bridge. The A3946 is available in a choice of two power packages: a 16-lead SOIC with copper batwing power tab (part number suffix LB), and a 16-lead TSSOP with exposed thermal pad (suffix LP). Scale 1:1 GH BOOT 10 IN1 9 ~FAULT A3946KLP TSSOP with Exposed Thermal Pad VREG CP2 CP1 PGND GL S GH 1 2 3 4 5 6 7 8 16 VBB 15 VREF 14 DT 13 LGND 12 RESET 11 IN2 10 IN1 9 ~FAULT www.DataSheet4U.com Scale 1:1 BOOT FEATURES On-chip charge pump for 7 V minimum input supply voltage High-current gate drive for driving a wide range of N-channel MOSFETs Bootstrapped gate drive with charge pump for 100% duty cycle Overtemperature protection Undervoltage protection –40ºC to 135ºC ambient operation ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB ............................. 60 V Logic Inputs ..................................–0.3 V to 6.5 V Pin S……. .........................................–4 V to 60 V Pin GH ...........................................–4 V to 75 V Pin BOOT….. ................................–0.6 V to 75 V Pin DT ........................................................ VREF Pin VREG ......................................–0.6 V to 15 V Package Thermal Resistance, RJA A3946KLB..................................... 48°C/W1 A3946KLB..................................... 38°C/W2 A3946KLP ..................................... 44°C/W1 A3946KLP ..................................... 34°C/W2 Operating Temperature Range, TA .. –40°C to +135°C Junction Temperature, TJ...........................+150°C Storage Temperature Range, TS ....-55°C to +150°C Always order by complete part number: Part Number A3946KLB A3946KLP Package 16-Lead SOIC; Copper Batwing Power Tab 16-Lead TSSOP; Exposed Thermal Pad Notes: 1. Measured on a two-sided PCB with 3 in.2 of 2 oz. copper. 2. Measured on JEDEC standard High-K board. Data Sheet 29319.150 3946 Half-Bridge Power MOSFET Controller Functional Block Diagram +VBAT C1 0.47 uF, X7R V rated to VBAT C2 0.47 uF, X7R V rated to VBAT P VBB CP2 CP1 VREF +5 Vref 0.1 uF X7R 10 V L Charge Pump ILIM VREG CREG P 10 kΩ L P Charge Pump BOOT ~FAULT Protection VREG Undervoltage Overtemperature UVLOBOOT L VREF DT Turn-On Delay High Side Driver GH RGATE P Bootstrap UVLO CBOOT RDEAD L IN1 Control Logic VREG L S IN2 Low Side Driver GL RGATE PGND L RESET P L LGND L P Control Logic Table IN1 X 0 0 1 1 0 0 1 1 IN2 X 0 1 0 1 0 1 0 1 DT Pin X RDEAD - LGND RDEAD - LGND RDEAD - LGND RDEAD - LGND VREF VREF VREF VREF RESET 0 1 1 1 1 1 1 1 1 GH Z L L L H L L H H GL Z H L L L L H L H Sleep mode Low-side FET ON following dead time All OFF All OFF High-side FET ON following dead time All OFF Low-side FET ON High-side FET ON CAUTION: High-side and low-side FETs ON Function www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Data Sheet 29319.150 3946 Half-Bridge Power MOSFET Controller ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted) Characteristics Symbol Test Conditions RESET = High, Outputs Low RESET = Low VBB > 7.75 V, Ireg = 0 mA to 15 mA VBB = 7 V to 7.75 V, Ireg = 0 mA to 15 mA CP1, CP2 IREF ≤ 4 mA, CREF = 0.1 µF Limits Min. Typ. 3 Max. 6 10 13.5 13.5 Units mA µA V V kHz V VBB Quiescent Current IVBB – – 12.0 11.0 – 13 VREG Output Voltage Charge Pump Frequency VREF Output Voltage VREG FCP VREF – 62.5 – 4.5 – 5.5 – 60 40 4 6 2 3 Gate Output Drive Turn On Time Turn Off Time Pullup On Resistance trise tfall RDSUP CLOAD = 3300 pF, 20% to 80% CLOAD = 3300 pF, 80% to 20% Tj = 25°C Tj = 135°C Tj = 25°C Tj = 135°C tpw < 10 µs tpw < 10 µs tpw < 10 µs, Bootstrap Capacitor fully charged Pulldown On Resistance Short Circuit Current – Source Short Circuit Current – Sink GH Output Voltage GL Output Voltage RDSDOWN – – – – – – 800 1000 VREG – 1.5 VREG – 0.2 100 80 ns ns Ω Ω Ω Ω mA mA V V – – – – – – – – 500 7 150 – – VGH VGL – – – – 350 6 – Rdead = 5 kΩ Rdead = 100 kΩ Logic input to unloaded GH, GL. DT = VREF Timing Dead Time (Delay from Turn Off to Turn On) Propagation Delay tDEAD tPD 200 5 ns µs ns – – www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Data Sheet 29319.150 3946 Half-Bridge Power MOSFET Controller ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted) Limits Characteristics Protection VREG Undervoltage VREG Undervoltage BOOT Undervoltage BOOT Undervoltage Thermal Shutdown Temperature Thermal Shutdown Hysteresis VREGON VREGOFF VBSON VBSOFF TJTSD ∆TJ VREG increasing VREG decreasing VBOOT increasing VBOOT decreasing Temperature increasing Recovery = TJTSD – ∆TJ 8.6 7.8 8 7.25 9.1 8.3 8.75 8.0 170 15 9.6 8.8 9.5 8.75 V V V V °C °C Symbol Test Conditions Min. Typ. Max. Units – – – – – 2.0 2.2 – – 100 40 1 Logic Input Current IIN(1) IIN(0) IN1 VIN / IN2 VIN = 2.0 V IN1 VIN / IN2 VIN = 0.8 V RESET pin only Logic Input Voltage VIN(1) IN1 / IN2 logic high RESET logic high VIN(0) Logic Input Hysteresis Fault Output Logic low All digital inputs I = 1 mA, fault asserted V=5V 40 16 µA µA µA V V V mV mV µA – 100 – Vol Voh – – – – – – – – – – – 0.8 300 400 1 www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Data Sheet 29319.150 3946 Half-Bridge Power MOSFET Controller Functional Description VREG. A 13 V output from the on-chip charge pump, used to power the low-side gate drive circuit directly, provides the current to charge the bootstrap capacitors for the high-side gate drive. The VREG capacitor, CREG, must supply the instantaneous current to the gate of the low-side MOSFET. A 10 µF, 25 V capacitor should be adequate. This capacitor can be either electrolytic or ceramic (X7R). Diagnostics and Protection. The fault output pin, ~FAULT, goes low (i.e., FAULT = 1) when the RESET line is high and any of the following conditions are present: • Undervoltage conditions on VREG (UVREG) or on the internal logic supply VREF (UVREF). These conditions set a latched fault. • A junction temperature > 170°C (OVERTEMP). This condition sets a latched fault. • An undervoltage on the stored charge of the BOOT capacitor (UVBOOT). This condition does NOT set a latched fault. An overtemperature event signals a latched fault, but does not disable any output drivers, regulators, or logic inputs. The user must turn off the A3946 (e.g., force the RESET line low) to prevent damage. The power FETs are protected from inadequate gate drive voltage by undervoltage detectors. Either of the regulator undervoltage faults (UVREG or UVREF) disable both output drivers until both voltages have been restored. The high-side driver is also disabled during a UVBOOT fault condition. Under many operating conditions, both the high-side (GH) and low-side (GL) drivers may be off, allowing the BOOT capacitor to discharge (or never become charged) and create a UVBOOT fault condition, which in turn inhibits the highside driver and creates a FAULT = 1. This fault is NOT latched. To remove this fault, momentarily turn on GL to charge the BOOT capacitor. Latched faults may be cleared by a low pulse, 1 to 10 µs wide, on the RESET line. Throughout that pulse (despite a possible UVBOOT), FAULT = 0; also the fault latch is cleared immediately, and remains cleared. If the power is restored (no UVREG or UVREF), and if no OVERTEMP fault exists, then the latched fault remains cleared when the RESET line returns to high. However, FAULT = 1 may still occur because a UVBOOT fault condition may still exist. Charge Pump. The A3946 is designed to accommodate a wide range of power supply voltages. The charge pump output, VREG, is regulated to 13 V nominal. In all modes, this regulator is current-limited. When VBB < 8 V, the charge pump operates as a voltage doubler. When 8 V < VBB< 15 V, the charge pump operates as a voltage doubler/PWM, current-controlled, voltage regulator. When VBB>15 V, the charge pump operates as a PWM, current-controlled, voltage regulator. Efficiency shifts, from 80% at VBB= 7 V, to 20% at VBB = 50 V. CAUTION. Although simple paralleling of VREG supplies from several A3946s may appear to work correctly, such a configuration is NOT recommended. There is no assurance that one of the regulators will not dominate, taking on all of the load and back-biasing the other regulators. (For example, this could occur if a particular regulator has an internal reference voltage that is higher that those of the other regulators, which would force it to regulate at the highest voltage.) Sleep Mode/Power Up. In Sleep Mode, all circuits are disabled in order to draw minimum current from VBB. When powering up and leaving Sleep Mode (the RESET line is high), the gate drive outputs stay disabled and a fault remains asserted until VREF and VREG pass their undervoltage thresholds. When powering up, before starting the first bootstrap charge cycle, wait until t = CREG ⁄ 4 (where