Multiple Switch Detection Interface

Freescale Semiconductor Advance Information Document Number: MC33993 Rev. 4.0, 6/2007 Multiple Switch Detection Interface The 33993 Multiple Switch Detection Interface is designed to detect the closing and opening of up to 22 switch contacts. The switch status, either open or closed, is transferred to the microprocessor unit (MCU) through a serial peripheral interface (SPI). The device also features a 22-to-1 analog multiplexer for reading inputs as analog. The analog input signal is buffered and provided on the AMUX output pin for the MCU to read. 33993 MULTIPLE SWITCH DETECTION INTERFACE www.DataSheet4U.com The 33993 device has two modes of operation, Sleep and Normal. The Sleep mode provides low quiescent current and enables the wake-up features of the device. Normal mode allows programming of the device and supplies switch contacts with pull-up or pull-down DW SUFFIX current as it monitors switch change of state. EK SUFFIX (PB-FREE) 98ARH99137A The 33993 is packaged in the 32-pin wide-body SOIC, reducing 32-PIN SOICW circuit board area. Low quiescent current makes the 33993 ideal for automotive and industrial products requiring low sleep state currents. ORDERING INFORMATION Features Temperature • Designed to Operate 5.5 V ≤ VPWR ≤ 26 V Device Package Range (TA) • Switch Input Voltage Range -14 V to VPWR, 40 V Max MC33993DWB/R2 • Interfaces Directly to Microprocessor Using 3.3 V / 5.0 V SPI -40°C to 125°C 32 SOICW Protocol MCZ33993EW/R2 • Selectable Wake-Up on Change of State • Selectable Wetting Current (16 mA or 2.0 mA) • 8 Programmable Inputs (Switches to Battery or Ground) • 14 Switch-to-Ground Inputs • VPWR Standby Current 100 µA Typical, VDD Standby Current 20 µA Typical • Active Interrupt (INT) on Change-of-Switch State • Pb-Free Packaging Designated by Suffix Code EW VDD VBAT Power Supply LVI VBAT SP0 SP1 VBAT SP7 33993 VPWR VDD VDD WAKE SI SCLK CS SO INT AMUX Enable Watchdog Reset MCU SG0 SG1 MOSI SCLK CS MISO INT AN0 SG12 GND SG13 Figure 1. MC33993 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2003-2007. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM 5.0 V VPWR VPWR 16.0 mA SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7 16.0 mA To + 2.0 4.0 V – SPI mA Ref Comparator VPWR VPWR 16.0 mA 2.0 mA Oscillator and Clock Control SP7 5.0 V VPWR 16.0 mA To + 2.0 4.0 V – SPI mA Ref Comparator 2.0 mA SP0 VPWR VPWR, VDD, 5.0 V POR Bandgap Sleep PWR VPWR VDD GND 5.0 V 5.0 V VPWR 5.0 V WAKE Temperature Monitor and Control VPWR VPWR 16.0 mA SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 2.0 mA SG0 5.0 V 125 kΩ To + 4.0 V – SPI Ref Comparator WAKE Control VDD SPI Interface and Control 125 kΩ INT INT Control VDD MUX Interface 40 µA CS SCLK SI SO VDD SG10 SG11 SG12 SG13 To + 4.0 V – SPI Ref Comparator VPWR VPWR 16.0 mA 2.0 mA VDD SG13 + Analog Mux Output – AMUX Figure 2. 33993 Simplified Internal Block Diagram 33993 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS GND SI SCLK CS SP0 SP1 SP2 SP3 SG0 SG1 SG2 SG3 SG4 SG5 SG6 VPWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SO VDD AMUX INT SP7 SP6 SP5 SP4 SG7 SG8 SG9 SG10 SG11 SG12 SG13 WAKE Figure 3. 33993 Pin Connections Table 1. 33993 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9. Pin Number 1 2 3 4 5–8 25 – 28 9 – 15, 18 – 24 16 17 29 30 31 32 Pin Name GND SI SCLK CS SP0 – 3 SP4 – 7 SG0 – 6, SG13 – 7 VPWR WAKE INT AMUX VDD SO Formal Name Ground SPI Slave In Serial Clock Chip Select Programmable Switches 0–7 Switch-to-Ground Inputs 0 – 13 Battery Input Wake-Up Interrupt Analog Multiplex Output Voltage Drain Supply SPI Slave Out Definition Ground for logic, analog, and switch to battery inputs. SPI control data input pin from MCU to the 33993. SPI control clock input pin. SPI control chip select input pin from MCU to the 33993. Logic 0 allows data to be transferred in. Programmable switch-to-battery or switch-to-ground input pins. Switch-to-ground input pins. Battery supply input pin. Pin requires external reverse battery protection. Open drain wake-up output. Designed to control a power supply enable pin. Open-drain output to the MCU. Used to indicate an input switch change of state. Analog multiplex output. 3.3 / 5.0 V supply. Sets SPI communication level for the SO driver. Provides digital data from 33993 to the MCU. 33993 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS VDD Supply Voltage CS, SI, SO, SCLK, INT, AMUX (1) WAKE (1) Symbol Value Unit – – – – – – -0.3 to 7.0 -0.3 to 7.0 -0.3 to 40 -0.3 to 50 -14 to 40 6.0 VDC VDC VDC VDC VDC MHz V VPWR Supply Voltage (1) Switch Input Voltage Range Frequency of SPI Operation (VDD = 5.0 V) ESD Voltage (2) Human Body Model Machine Model THERMAL RATINGS Storage Temperature Operating Case Temperature Operating Junction Temperature THERMAL RESISTANCE Power Dissipation (TA = 25°C) (3) Thermal Resistance Junction to Ambient Junction to Lead Peak Package Reflow Temperature During Reflow (4), (5) VESD1 VESD2 ±4000 ±200 TSTG TC TJ -55 to 150 -40 to 125 -40 to 150 °C °C °C PD 1.7 W °C/W RθJA RθJL TPPRT 74 25 Note 5 °C Notes 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 3. 4. 5. Maximum power dissipation at TJ =150°C junction temperature with no heat sink used. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33993 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means VPWR = 13 V, TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER INPUT Supply Voltage Supply Voltage Range Quasi-Functional Fully Operational Supply Voltage Range Quasi-Functional Supply Current All Switches Open, Normal Mode, Tri-State Disabled Sleep State Supply Current Scan Timer = 64 ms, Switches Open Logic Supply Voltage Logic Supply Current All Switches Open, Normal Mode Sleep State Logic Supply Current Scan Timer = 64 ms, Switches Open SWITCH INPUT Pulse Wetting Current Switch-to-Battery (Current Sink) Pulse Wetting Current Switch-to-Ground (Current Source) Sustain Current Switch-to-Battery Input (Current Sink) Sustain Current Switch-to-Ground Input (Current Source) Sustain Current Matching Between Channels on Switch-to-Ground Inputs ISUS(MAX) - ISUS(MIN) X 100 ISUS(MIN) Input Offset Current when Selected as Analog Input Offset Voltage when Selected as Analog V(SP&SGINPUTS) to AMUX Output Analog Operational Amplifier Output Voltage Sink 250 µA Analog Operational Amplifier Output Voltage Source 250 µA Switch Detection Threshold Switch Input Voltage Range Temperature Monitor (7) (8) (6) (6) Symbol Min Typ Max Unit V VPWR (QF) VPWR (FO) VPWR (QF) IPWR (ON) – IPWR (SS) 40 VDD IDD – IDD(SS) – 10 20 0.25 0.5 µA 3.1 70 – 100 5.25 V mA 2.0 4.0 µA 5.5 8.0 26 – – – 8.0 26 40 mA IPULSE IPULSE ISUSTAIN ISUSTAIN IMATCH 12 12 1.8 1.8 15 16 2.0 2.0 18 18 2.2 2.2 mA mA mA mA % – 2.0 4.0 IOFFSET VOFFSET -2.0 1.4 2.0 µA mV -10 VOL – VOH VDD - 0.1 VTH VIN TLIM 3.70 -14 155 5.0 2.5 10 mV 10 30 V – 4.0 – – 10 – 4.3 40 185 15 V V , °C °C Temperature Monitor Hysteresis (8) TLIM(HYS) Notes 6. Device operational. Table parameters may be out of specification. 7. Thermal shutdown of 16 mA pull-up and pull-down current sources only. 2.0 mA current source / sink and all other functions remain active. 8. This parameter is guaranteed by design but is not production tested. 33993 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means VPWR = 13 V, TA = 25°C under nominal conditions unless otherwise noted. Characteristic DIGITAL INTERFACE Input Logic Voltage Thresholds (9) SCLK, SI, Tri-State SO Input Current 0 V to VDD CS Input Current CS = VDD CS Pull-Up Current CS = 0 V Symbol Min Typ Max Unit VINLOGIC ISCLK, ISI, ISO (TRI) ICS 0.8 – 2.2 V µA -10 – 10 µA -10 ICS 30 VSO (HIGH) VDD - 0.8 VSO (LOW) – CIN – V INT (HIGH) VDD - 0.5 V INT (LOW) – I WAKE (PU) V WAKE (HIGH) 4.0 V WAKE(LOW) – V WAKE(MAX) – 20