DATA SHEET
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MOS FIELD EFFECT TRANSISTOR
2SK3113
SWITCHING N-CHANNEL POWER MOS FET
DESCRIPTION
The 2SK3113 is N-channel DMOS FET device that features a low gate charge and excellent switching characteristic, and designed for high voltage applications such as switching power supply, AC adapter.
ORDERING INFORMATION
PART NUMBER 2SK3113 2SK3113-Z PACKAGE TO-251 (MP-3) TO-252 (MP-3Z)
FEATURES
• Low on-state resistance RDS(on) = 4.4 Ω MAX. (VGS = 10 V, ID = 1.0 A) • Low gate charge QG = 9 nC TYP. (VDD = 450 V, VGS = 10 V, ID = 2.0 A) • Gate voltage rating ±30 V • Avalanche capability ratings (TO-251)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25°C) Drain Current (pulse)
Note1
VDSS VGSS ID(DC) ID(pulse) PT1
Note2
600
V V A A W W °C °C A mJ (TO-252)
±30 ±2.0 ±8.0 20 1.0 150 –55 to +150 2.0 2.7
Total Power Dissipation (TC = 25°C) Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy
Note3 Note3
PT2 Tch Tstg IAS EAS
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1% 2. Mounted on glass epoxy board of 40 mm x 40 mm x 1.6 mm 3. Starting Tch = 25°C, VDD = 150 V, RG = 25 Ω, VGS = 20 → 0 V
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. D13336EJ3V0DS00 (3rd edition) Date Published August 2004 NS CP(K) Printed in Japan
The mark
shows major revised points.
1998, 2001
2SK3113
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge SYMBOL IDSS IGSS VGS(off) | yfs | RDS(on) Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr VDD = 450 V VGS = 10 V ID = 2.0 A IF = 2.0 A, VGS = 0 V IF = 2.0 A, VGS = 0 V di/dt = 50 A/µs TEST CONDITIONS VDS = 600 V, VGS = 0 V VGS = ±30 V, VDS = 0 V VDS = 10 V, ID = 1 mA VDS = 10 V, ID = 1.0 A VGS = 10 V, ID = 1.0 A VDS = 10 V VGS = 0 V f = 1 MHz VDD = 150 V, ID = 1.0 A VGS = 10 V RG = 10 Ω, RL = 10 Ω 2.5 0.5 3.3 290 60 5 7 2 22 9 9 2.4 2 0.9 0.9 2.0 4.4 MIN. TYP. MAX. 100 ±10 3.5 UNIT
µA µA
V S Ω pF pF pF ns ns ns ns nC nC nC V
µs µC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V BVDSS VDS VGS 0 50 Ω L VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T. RL PG. RG VDD ID
90% 90%
VGS VGS
Wave Form
0
10%
VGS
90%
IAS ID VDD
ID ID
Wave Form
0 10%
10%
τ Starting Tch τ = 1 µs Duty Cycle ≤ 1%
td(on) ton
tr
td(off) toff
tf
TEST CIRCUIT 3 GATE CHARGE
D.U.T. IG = 2 mA 50 Ω RL VDD
PG.
2
Data Sheet D13336EJ3V0DS
2SK3113
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100
dT - Percentage of Rated Power - %
PT - Total Power Dissipation - W
TOTAL POWER DISSIPATION vs. CASE TEMPERATURE 40 35 30 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 Mounted on glass epoxy board of 40 mm x 40 mm x 1.6 mm
80
60
40
20
0 0
20
40
60
80
100
120 140
160
Tch - Channel Temperature - ˚C
TC - Case Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA 100
TC = 25˚C, Single pulse Mounted on glass epoxy board of 40 mm x 40 mm x 1.6 mm
=2 S 0V )
ID - Drain Current - A
10
a d(
ID(pulse)
10 0
PW
=
10
G tV
µs
1
R
n) (o DS
Lim
ite
ID(DC)
10 Di 0 ss m ipa s tio DC n Lim ite d
µs
1
Po we r
m s
10
m s
0.1 1
10
100
1000
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
Rth(ch-A) = 125˚C/W 100
10 Rth(ch-C) = 6.25˚C/W 1
0.1 Single pulse Mounted on glass epoxy board of 40 mm x 40 mm x 1.6 mm 10 100 1000
0.01 10 µ
100 µ
1m
10 m
100 m
1
PW - Pulse Width - s
Data Sheet D13336EJ3V0DS
3
2SK3113
DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE Pulsed 5 4 3 2 1 VGS = 10 V 6V 8V
ID - Drain Current - A
FORWARD TRANSFER CHARACTERISTICS
100 Tch = 125˚C 75˚C 10
ID - Drain Current - A
1.0
Tch = 25˚C −25˚C
0.1 VDS = 10 V Pulsed 15
0
0
0
10
20
30
40
0
5
10
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT
| yfs | - Forward Transfer Admittance - S
5.0
VGS(off) - Gate Cut-off Voltage - V
100
VDS = 10 V Pulsed
4.0
10 Tch = −25˚C 25˚C 75˚C 125˚C
3.0
2.0
1
1.0 VDS = 10 V ID = 1 mA 0 −50 0 50 100 150
0.1 0.01
0.1
1.0
10
Tch - Channel Temperature - ˚C
ID - Drain Current - A
RDS(on) - Drain to Source On-state Resistance - Ω
RDS(on) - Drain to Source On-state Resistance - Ω
DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 7 6 5 4 3 2 1 0 0 5 10 15 ID = 2.0 A 1.0 A Pulsed
DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT Pulsed 7 6 5 4 3 2 1 0 0.1 1 ID - Drain Current - A 10 VGS = 10 V 20 V
VGS - Gate to Source Voltage - V
4
Data Sheet D13336EJ3V0DS
2SK3113
RDS(on) - Drain to Source On-state Resistance - Ω
DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 9
IF - Diode Forward Current - A
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
8 7 6 5 4 3 2 1 1A
ID = 2 A
100
10
1.0 VGS = 10 V 0.1 0V Pulsed 1.5
VGS = 10 V 0 −50 0 50 100 150
0 0.5 1.0
Tch - Channel Temperature - ˚C
VF(S-D) - Source to Drain Voltage - V
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 100 10000
SWITCHING CHARACTERISTICS
td(on), tr, td(off), tf - Switching Time - ns
Ciss, Coss, Crss - Capacitance - pF
td(off) 10 tf td(on) tr 1 VDD = 150 V VGS = 10 V RG = 10 Ω 1 ID - Drain Current - A 10
1000 Ciss 100 Coss 10 VGS = 0 V f = 1 MHz 1 0.1 1 10 Crss 100
0.1 0.1
VDS - Drain to Source Voltage - V
REVERSE RECOVERY TIME vs. DRAIN CURRENT 10000
trr - Reverse Recovery Time - ns VDS - Drain to Source Voltage - V
600
1000
VDD = 450 V 300 V 150 V
VGS
12 10 8 6
400
100
200 VDS 0 0 4 8 12
4 2 0 16
10 0.1
1.0
10
100
ID - Drain Current - A
QG - Gate Charge - nC
Data Sheet D13336EJ3V0DS
VGS - Gate to Source Voltage - V
di/dt = 50 A/µs VGS = 0 V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS 16 800 ID = 2.0 A 14
5
2SK3113
SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD 100
120
SINGLE AVALANCHE ENERGY DERATING FACTOR VDD = 150 V RG = 25 Ω VGS = 20 → 0 V IAS ≤ 2.0 A
IAS - Single Avalanche Current - A
Energy Derating Factor - %
100 80 60 40 20 0 25
10 IAS = 2.0 A 1.0 RG = 25 Ω VDD = 150 V VGS = 20 → 0 V Starting Tch = 25˚C 0.1 10 µ 100 µ 1m 10 m
EAS
=2
.7 m
J
50
75
100
125
150
L - Inductive Load - H
Starting Tch - Starting Channel Temperature - ˚C
6
Data Sheet D13336EJ3V0DS
2SK3113
PACKAGE DRAWINGS (Unit: mm)
1) TO-251 (MP-3)
2) TO-252 (MP-3Z)
1.5 −0.1
+0.2
5.0 ±0.2
1.6 ±0.2
0.5 ±0.1
0.8 4.3 MAX.
4
5.5 ±0.2 13.7 MIN.
6.5 ±0.2 5.0 ±0.2 4
1.5 −0.1
+0.2
6.5 ±0.2
2.3 ±0.2
2.3 ±0.2 0.5 ±0.1
1
2
3
7.0 MIN.
1
2
3
1.1 ±0.2
+0.2
0.5 −0.1
2.3 2.3
0.75
0.5 −0.1
1. Gate 2. Drain 3. Source 4. Fin (Drain)
+0.2
0.9 0.8 2.3 2.3 MAX. MAX. 0.8 1. Gate 2. Drain 3. Source 4. Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Gate
Body Diode
Gate Protection Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.
0.7
1.1 ±0.2
2.0 MIN.
5.5 ±0.2 10.0 MAX.
1.0 MIN. 1.8TYP.
Data Sheet D13336EJ3V0DS
7
2SK3113
• The information in this document is current as of August, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in
