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Features
• Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes 0 Operation
• 33 MHz Clock Rate • Byte Mode and 128-byte Page Mode for Program Operations • Sector Architecture: • • • • • • • • •
– Two Sectors with 32K Bytes Each – 256 Pages per Sector Product Identification Mode Low-voltage Operation – 2.7 (VCC = 2.7 to 3.6V) Sector Write Protection Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection Self-timed Program Cycle (75 µs/byte typical) Self-timed Sector Erase Cycle (1 second/sector typical) Single Cycle Reprogramming (Erase and Program) for Status Register High Reliability – Endurance: 10,000 Write Cycles Typical – Data Retention: 20 Years 8-lead JEDEC SOIC and 8-lead SAP Packages
512Kbit High Speed SPI Serial Flash Memory
512K (65,536 x 8)
Description
The AT25F512A provides 524,288 bits of serial reprogrammable Flash memory organized as 65,536 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F512A is available in a space-saving 8-lead JEDEC SOIC and 8-lead SAP packages. The AT25F512A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. Block write protection for the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the Write Protect (WP) pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configuration
Pin Name CS SCK SI SO GND VCC WP HOLD Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input
8-lead SAP VCC HOLD SCK SI 8 7 6 5 1 2 3 4 CS SO WP GND CS SO WP GND 8-lead SOIC 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
AT25F512A
Bottom View
Rev. 3345F–FLASH–11/06
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Absolute Maximum Ratings*
Operating Temperature........................................−40°C to +85°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +5.0V Maximum Operating Voltage ............................................ 4.2V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
65,536 x 8
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AT25F512A
Table 2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 20 MHz, VCC = +3.6V (unless otherwise noted)
Symbol COUT CIN Note: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V
Table 3. DC Characteristics(1) Applicable over recommended operating range from: TAI = −40 to +85°C, VCC = +2.7 to +3.6V, TAC = 0 to +70°C, VCC = +2.7 to +3.6V (unless otherwise noted)
Symbol VCC ICC1 ICC2 ISB IIL IOL VIL(2) VIH(2) VOL VOH Notes: Parameter Supply Voltage Supply Current Supply Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.7V ≤ VCC ≤ 3.6V IOL = 0.15 mA IOH = −100 µA VCC − 0.2 VCC = 3.6V at 33 MHz, SO = Open Read VCC = 3.6V at 33 MHz, SO = Open Write VCC = 2.7V, CS = VCC; SCK, SI, WP, HOLD = 0V or VCC VIN = 0V or VCC VIN = 0V or VCC, TAI = −40°C to 85°C −3.0 −3.0 −0.6 VCC x 0.7 Test Condition Min 2.7 10.0 25.0 2.0 Typ Max 3.6 15.0 35.0 10.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.2 Units V mA mA µA µA µA V V V V
1. Preliminary – subject to change 2. VIL and VIH max are reference only and are not tested.
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Table 4. AC Characteristics (Preliminary - Subject to Change) Applicable over recommended operating range from TAI = −40 to +85°C, VCC = +2.7 to +3.6V CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol fSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tHD tCD tV tHO tLZ tHZ tDIS tEC tSR tBPC Endurance(2) Notes: Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Hold Setup Time Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Erase Cycle Time per Sector Status Register Write Cycle Time Byte Program Cycle Time(1) 75 10K 0 200 200 100 1.1 60 100 9 9 25 25 10 5 5 15 15 9 Min 0 Typ Max 33 20 20 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms µs Write Cycles(3)
1. The programming time for n bytes will be equal to n x tBPC. 2. This parameter is ensured by characterization at 3.0V, 25°C only. 3. One write cycle consists of erasing a sector, followed by programming the same sector.
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AT25F512A
MASTER: The device that generates the serial clock. SLAVE: Because the SCK pin is always an input, the AT25F512A always operates as a slave. TRANSMITTER/RECEIVER: The AT25F512A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25F512A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25F512A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F512A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The AT25F512A has a write lockout feature that can be activated by asserting the WP pin. When the lockout feature is activated, locked-out sectors will be read only. The write protect pin will allow normal read/write operations when held high. When the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal status register write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25F512A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.
Serial Interface Description
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Figure 2. SPI Serial Interface
MASTER: MICROCONTROLLER DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SLAVE: AT25F512A SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS
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w w w . D a t a S h e e t 4 U . c o m
AT25F512A
Functional Description
The AT25F512A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25F512A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification. The commands Program, Sector Erase, Chip Erase, and WRSR are write instructions for AT25F512A. Table 5. Instruction Set for the AT25F512A
Instruction Name WREN WRDI RDSR WRSR READ PROGRAM SECTOR ERASE CHIP ERASE RDID Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 0101 X010 0110 X010 0001 X101 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Program Data into Memory Array Erase One Sector in Memory Array Erase All Sectors in Memory Array Read Manufacturer and Product ID
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The RDSR instru
