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XC9572 Datasheet

XC9572 In-System Programmable CPLD


XC9572 Datasheet Preview


– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
0
R XC9572 In-System
Programmable CPLD
DS065 (v5.0) May 17, 2013
05
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP,
and 100-pin TQFP packages
Product Specification
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9572 device.
200
(125)
100
(65)
High Performance
Low Power
(160)
(100)
0 50 100
Clock Frequency (MHz)
DS065_01_110501
Figure 1: Typical ICC vs. Frequency for XC9572
© 1998, 2003–2006, 2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS065 (v5.0) May 17, 2013
Product Specification
www.xilinx.com
1
Page 1

– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
XC9572 In-System Programmable CPLD
JTAG Port
3
1
JTAG
Controller
In-System Programming Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
3
1
2
I/O
Blocks
36
18
36
18
36
18
36
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
Function
Block 3
Macrocells
1 to 18
Function
Block 4
Macrocells
1 to 18
R
Figure 2: XC9572 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
DS065_02_110101
2
www.xilinx.com
DS065 (v5.0) May 17, 2013
Product Specification
Page 2

– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R XC9572 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
Description
Value
Units
VCC Supply voltage relative to GND
–0.5 to 7.0
V
VIN Input voltage relative to GND
–0.5 to VCC + 0.5
V
VTS
TSTG
TJ
Voltage applied to 3-state output
Storage temperature (ambient)
Junction temperature
–0.5 to VCC + 0.5
–65 to +150
+150
V
oC
oC
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
VCCINT
VCCIO
VIL
VIH
VO
Parameter
Supply voltage for internal logic
and input buffers
Supply voltage for output drivers
for 5V operation
Commercial TA = 0oC to 70oC
Industrial TA = –40oC to +85oC
Commercial TA = 0oC to 70oC
Industrial TA = –40oC to +85oC
Supply voltage for output drivers for 3.3V operation
Low-level input voltage
High-level input voltage
Output voltage
Min
4.75
4.5
4.75
4.5
3.0
0
2.0
0
Max
5.25
5.5
5.25
5.5
3.6
0.80
VCCINT + 0.5
VCCIO
Units
V
V
V
V
V
Quality and Reliability Characteristics
Symbol
Parameter
TDR Data Retention
NPE Program/Erase Cycles (Endurance)
Min Max Units
20 - Years
10,000 - Cycles
DC Characteristic Over Recommended Operating Conditions
Symbol
VOH
VOL
IIL
Parameter
Output high voltage for 5V outputs
Output high voltage for 3.3V outputs
Output low voltage for 5V outputs
Output low voltage for 3.3V outputs
Input leakage current
IIH I/O high-Z leakage current
CIN I/O capacitance
ICC Operating supply current
(low power mode, active)
Test Conditions
IOH = –4.0 mA, VCC = Min
IOH = –3.2 mA, VCC = Min
IOL = 24 mA, VCC = Min
IOL = 10 mA, VCC = Min
VCC = Max
VIN = GND or VCC
VCC = Max
VIN = GND or VCC
VIN = GND
f = 1.0 MHz
VI = GND, No load
f = 1.0 MHz
Min Max
2.4 -
2.4 -
- 0.5
- 0.4
- ±10
- ±10
- 10
65 (Typical)
Units
V
V
V
V
μA
μA
pF
mA
DS065 (v5.0) May 17, 2013
Product Specification
www.xilinx.com
3
Page 3
Part Number XC9572
Manufactur Xilinx
Description XC9572 In-System Programmable CPLD
Total Page 9 Pages
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