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XC95108 Datasheet

XC95108 In-System Programmable CPLD


XC95108 Datasheet Preview


1
® XC95108 In-System Programmable
CPLD
December 4, 1998 (Version 3.0)
1 1* Product Specification
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 108 macrocells with 2400 usable gates
• Up to 108 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP
and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
300
200
(180)
100
High Performance
Low Power
(250)
(170)
0 50 100
Clock Frequency (MHz)
X5898
Figure 1: Typical ICC vs. Frequency for XC95108
December 4, 1998 (Version 3.0)
1
Page 1

XC95108 In-System Programmable CPLD
JTAG Port
3
1
JTAG
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
3
1
2
I/O
Blocks
In-System Programming Controller
36
18
36
18
36
18
36
18
36
18
36
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
Function
Block 3
Macrocells
1 to 18
Function
Block 4
Macrocells
1 to 18
Function
Block 5
Macrocells
1 to 18
Function
Block 6
Macrocells
1 to 18
Figure 2: XC95108 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
X5897
2 December 4, 1998 (Version 3.0)
Page 2

XC95108 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
Parameter
Value
Units
VCC
VIN
VTS
TSTG
TSOL
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
-0.5 to 7.0
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
-65 to +150
+260
V
V
V
°C
°C
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions1
Symbol
Parameter
VCCINT
Supply voltage for internal logic and input buffer
VCCIO
VIL
VIH
VO
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
Note: 1. Numbers in parenthesis are for industrial-temperature range versions.
Min
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
Max
5.25
(5.5)
5.25 (5.5)
3.6
0.80
VCCINT +0.5
VCCIO
Units
V
V
V
V
V
V
Endurance Characteristics
Symbol
tDR
NPE
Parameter
Data Retention
Program/Erase Cycles
Min
20
10,000
Max
-
-
Units
Years
Cycles
December 4, 1998 (Version 3.0)
3
Page 3

XC95108 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
VOH
Output high voltage for 5 V operation
Output high voltage for 3.3 V operation
VOL Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
IIL Input leakage current
IIH I/O high-Z leakage current
CIN I/O capacitance
ICC Operating Supply Current
(low power mode, active)
Test Conditions
IOH = -4.0 mA
VCC = Min
IOH = -3.2 mA
VCC = Min
IOL = 24 mA
VCC = Min
IOL = 10 mA
VCC = Min
VCC = Max
VIN = GND or VCC
VCC = Max
VIN = GND or VCC
VIN = GND
f = 1.0 MHz
VI = GND, No load
f = 1.0 MHz
Min Max Units
2.4 V
2.4
0.5
V
V
0.4 V
±10.0 µA
±10.0 µA
10.0 pF
100 (Typ)
ma
AC Characteristics
Symbol
Parameter
XC95108-7 XC95108-10 XC95108-15 XC95108-20
Units
Min Max Min Max Min Max Min Max
tPD I/O to output valid
tSU I/O setup time before GCK
tH I/O hold time after GCK
tCO GCK to output valid
fCNT1
16-bit counter frequency
fSYSTEM 2 Multiple FB internal operating frequency
tPSU
I/O setup time before p-term clock input
tPH I/O hold time after p-term clock input
tPCO
P-term clock to output valid
tOE GTS to output valid
tOD GTS to output disable
tPOE
Product term OE to output enabled
tPOD
Product term OE to output disabled
tWLH
GCK pulse width (High or Low)
7.5 10.0 15.0 20.0 ns
4.5 6.0 8.0 10.0 ns
0.0 0.0 0.0 0.0 ns
4.5 6.0 8.0 10.0 ns
125.0
111.1
95.2
83.3
MHz
83.3
66.7
55.6
50.0
MHz
0.5 2.0 4.0 4.0 ns
4.0 4.0 4.0 6.0 ns
8.5 10.0 12.0 16.0 ns
5.5 6.0 11.0 16.0 ns
5.5 6.0 11.0 16.0 ns
9.5 10.0 14.0 18.0 ns
9.5 10.0 14.0 18.0 ns
4.0 4.5 5.5 5.5 ns
Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
4 December 4, 1998 (Version 3.0)
Page 4
Part Number XC95108
Manufactur Xilinx
Description XC95108 In-System Programmable CPLD
Total Page 8 Pages
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