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XC6SLX9 Datasheet

Spartan-6 FPGA


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73
DS162 (v1.9) August 23, 2010
Spartan-6 FPGA Data Sheet:
DC and Switching Characteristics
Advance Product Specification
Spartan-6 FPGA Electrical Characteristics
Spartan®-6 LX FPGAs are available in -3, -2, and -1L speed grades, with -3 having the highest performance. Spartan-6 LXT
FPGAs are available in -4, -3, and -2 speed grades, with -4 having the highest performance. Spartan-6 FPGA DC and AC
characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless
otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing
characteristics of a -2 speed grade industrial device are the same as for a -2 speed grade commercial device). However, only
selected speed grades and/or devices might be available in the industrial range. The -3N speed grade, designated for
Spartan-6 devices that do not support memory controller block (MCB) functionality, has identical timing characteristics to the
-3 speed grade.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters
included are common to popular designs and typical applications.
This Spartan-6 FPGA data sheet, part of an overall set of documentation on the Spartan-6 family of FPGAs, is available on
the Xilinx website.
All specifications are subject to change without notice.
Spartan-6 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings (1)
Symbol
Description
Units
VCCINT
VCCAUX
VCCO
VBATT
Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
Output drivers supply voltage relative to GND
Key memory battery backup supply (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only)
–0.5 to 1.32
–0.5 to 3.75
–0.5 to 3.75
–0.5 to 4.05
V
V
V
V
VFS
External voltage supply for eFUSE programming (XC6SLX75, XC6SLX75T, XC6SLX100,
XC6SLX100T, XC6SLX150, and XC6SLX150T only)(2)
–0.5 to 3.75
V
VREF
Input reference voltage
–0.5 to 3.75 V
DC –0.60 to 4.10 V
All user and dedicated
I/Os
Commercial 20% overshoot duration
8% overshoot duration(5)
DC
–0.75 to 4.25
–0.75 to 4.40
–0.60 to 3.95
V
V
V
VIN and VTS(3)
I/O input voltage or voltage
applied to 3-state output,
relative to GND(4)
Restricted to
maximum of 100 user
I/Os
Industrial
20% overshoot duration
4% overshoot duration(5)
20% overshoot duration
Commercial 15% overshoot duration(5)
10% overshoot duration
20% overshoot duration
Industrial
10% overshoot duration
8% overshoot duration(5)
–0.75 to 4.15
–0.75 to 4.40
–0.75 to 4.35
–0.75 to 4.40
–0.75 to 4.45
–0.75 to 4.25
–0.75 to 4.35
–0.75 to 4.40
V
V
V
V
V
V
V
V
© 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS162 (v1.9) August 23, 2010
Advance Product Specification
www.xilinx.com
1
Page 1

www.DataSheet4U.net
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 1: Absolute Maximum Ratings (1) (Cont’d)
Symbol
Description
Units
TSTG
TSOL
Tj
Storage temperature (ambient)
Maximum soldering temperature(6)
(TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256)
Maximum soldering temperature(6) (Pb-free packages: FGG484, FGG676, and FGG900)
Maximum soldering temperature(6) (Pb packages: FT256, FG484, FG676, and FG900)
Maximum junction temperature(6)
–65 to 150
+260
+250
+220
+125
°C
°C
°C
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. When programming eFUSE, VFS VCCAUX. Requires up to 40 mA current. For read mode, VFS can be between GND and 3.45 V.
3. I/O absolute maximum limit applied to DC and AC signals. Overshoot duration is the percentage of a data period that the I/O is stressed beyond
3.45V.
4. For I/O operation, refer to the Spartan-6 FPGA SelectIO Resources User Guide.
5. Maximum percent overshoot duration to meet 4.40V maximum.
6. For soldering guidelines and thermal considerations, see Spartan-6 FPGA Packaging and Pinout Specification.
Table 2: Recommended Operating Conditions(1)
Symbol
Description
Temperature Speed
Range
Grade
Memory
Controller
Block(2)
Performance
Internal supply voltage relative to GND, Commercial -4, -3, -2
Tj = 0°C to +85°C
standard
extended
VCCINT
Internal supply voltage relative to GND,
Tj = –40°C to +100°C
Industrial
-1L
-3, -2
standard
standard
extended
-1L standard
VCCAUX(3)
Auxiliary supply voltage relative to GND
when VCCAUX = 2.5V, Tj = 0°C to +85°C
Auxiliary supply voltage relative to GND
when VCCAUX = 2.5V, Tj = –40°C to
+100°C
Auxiliary supply voltage relative to GND
when VCCAUX = 3.3V, Tj = 0°C to +85°C
Auxiliary supply voltage relative to GND
when VCCAUX = 3.3V, Tj = –40°C to
+100°C
Commercial -4, -3, -2,
-1L
Industrial -3, -2, -1L
Commercial -4, -3, -2,
-1L
Industrial -3, -2, -1L
N/A
N/A
N/A
N/A
Output supply voltage relative to GND,
VCCO(4)(5)(6)
Tj = 0°C to +85°C
Output supply voltage relative to GND,
Tj = –40°C to +100°C
Input voltage relative to GND, Tj = 0°C to
+85°C
Commercial -4, -3, -2,
-1L
Industrial -3, -2, -1L
Commercial -4, -3, -2,
-1L
N/A
N/A
N/A
Input voltage relative to GND, Tj = –40°C Industrial -3, -2, -1L
to +100°C
VIN Input voltage relative to GND, PCI I/O Commercial -4, -3, -2,
standard, Tj = 0°C to +85°C
-1L(7)
Input voltage relative to GND, PCI I/O
standard, Tj = –40°C to +100°C
Industrial
-3, -2,
-1L(7)
N/A
N/A
N/A
Min
1.14
1.2
0.95
1.14
1.2
0.95
2.375
3.15
1.1
–0.5
–0.5
–0.5
–0.5
Typ Max Units
1.2 1.26 V
1.23 1.26 V
1.0 1.05 V
1.2 1.26 V
1.23 1.26 V
1.0 1.05 V
2.5 2.625 V
3.3 3.45 V
– 3.45 V
– 4.0 V
3.95 V
VCCO +
0.5
V
VCCO +
0.5
V
DS162 (v1.9) August 23, 2010
Advance Product Specification
www.xilinx.com
2
Page 2

www.DataSheet4U.net
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 2: Recommended Operating Conditions(1) (Cont’d)
Symbol
Description
Memory
Temperature Speed
Range
Grade
Controller
Block(2)
Min Typ Max Units
Performance
IIN(8)
Maximum current through pin using PCI
I/O standard when forward biasing the
clamp diode.
Commercial -4, -3, -2,
-1L(7)
Industrial
-3, -2,
-1L(7)
N/A
N/A
– – 10 mA
– – 10 mA
VBATT(9)
Battery voltage relative to GND, Tj = 0°C
to +85°C
(XC6SLX75, XC6SLX75T, XC6SLX100,
XC6SLX100T, XC6SLX150, and
XC6SLX150T only)
Battery voltage relative to GND,
Tj = –40°C to +100°C (XC6SLX75,
XC6SLX75T, XC6SLX100,
XC6SLX100T, XC6SLX150, and
XC6SLX150T only)
Commercial -4, -3, -2,
-1L
Industrial -3, -2, -1L
N/A
N/A
1.0 – 3.6 V
Notes:
1. All voltages are relative to ground.
2. See Interface Performances for Memory Interfaces in Table 25. The standard VCCINT voltage range applies to designs not using an MCB, or to devices
that do not support MCB functionality including the LX4 device, the TQG144 and CPG196 packages, and the -3N speed grade.
3. Recommended maximum voltage droop for VCCAUX is 10 mV/ms.
4. Configuration data is retained even if VCCO drops to 0V.
5. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
6. For PCI systems, the transmitter and receiver should have common supplies for VCCO.
7. Devices with a -1L speed grade do not support Xilinx PCI IP.
8. Do not exceed a total of 100 mA per bank.
9. VBATT is required to maintain the battery backed RAM (BBR) AES key when VCCAUX is not applied. Once VCCAUX is applied, VBATT can be
unconnected. When BBR is not used, Xilinx recommends connecting to VCCAUX or GND. However, VBATT can be unconnected.
Table 3: eFUSE Programming Conditions(1)
Symbol
Description
VFS(2) External voltage supply
IFS VFS supply current
VCCAUX Auxiliary supply voltage relative to GND
RFUSE(3) External resistor from RFUSE pin to GND
VCCINT Internal supply voltage relative to GND
tj Temperature range
Min Typ Max Units
3.2 3.3 3.4 V
– – 40 mA
3.2 3.3 3.45 V
1129 1140 1151 Ω
1.14 1.2 1.26 V
15 – 85 °C
Notes:
1. These specifications apply during programming of the eFUSE AES key. Programming is only supported through JTAG.The AES key is only supported
in the following devices: XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T.
2. When programming eFUSE, VFS must be less than or equal to VCCAUX. When not programming or when eFUSE is not used, Xilinx recommends
connecting VFS to GND. However, VFS can be between GND and 3.45 V.
3. An RFUSE resistor is required when programming the eFUSE AES key. When not programming or when eFUSE is not used, Xilinx recommends
connecting the RFUSE pin to VCCAUX or GND. However, RFUSE can be unconnected.
DS162 (v1.9) August 23, 2010
Advance Product Specification
www.xilinx.com
3
Page 3

www.DataSheet4U.net
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 4: DC Characteristics Over Recommended Operating Conditions
Symbol
Description
VDRINT
VDRAUX
IREF
IL
IHS
Data retention VCCINT voltage (below which configuration data might be lost)
Data retention VCCAUX voltage (below which configuration data might be lost)
VREF leakage current per pin
Input or output leakage current per pin (sample-tested)
Leakage current on pins during hot
socketing with FPGA unpowered
All pins except PROGRAM_B, DONE, and
JTAG pins when HSWAPEN = 1
PROGRAM_B, DONE, and JTAG pins, or other
pins when HSWAPEN = 0
CIN
IRPU
IRPD
IBATT(1)
RDT(2)
Die input capacitance at the pad
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V or VCCAUX = 3.3V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V or VCCAUX = 2.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Pad pull-down (when selected) @ VIN = VCCO, VCCAUX = 3.3V
Pad pull-down (when selected) @ VIN = VCCO, VCCAUX = 2.5V
Battery supply current
Resistance of optional input differential termination circuit, VCCAUX = 3.3V
Thevenin equivalent resistance of programmable input termination
(UNTUNED_SPLIT_25)
RIN_TERM(4)
Thevenin equivalent resistance of programmable input termination
(UNTUNED_SPLIT_50)
Thevenin equivalent resistance of programmable input termination
(UNTUNED_SPLIT_75)
Min Typ Max
0.8 –
2.0 –
–10 –
10
–10 –
10
–20 –
20
IHS + IRPU
– – 10
200 – 500
120 – 350
60 – 200
40 – 150
12 – 100
200 – 550
140 – 400
– – 150
– 100 –
23 25 55
39 50 72
56 75 109
Units
V
V
µA
µA
µA
µA
pF
µA
µA
µA
µA
µA
µA
µA
nA
Ω
Ω
Ω
Ω
Notes:
1. Maximum value specified for worst case process at 25°C. XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T
only.
2. Refer to IBIS models for RDT variation and for values at VCCAUX = 2.5V.
3. VCCO2 is not required for data retention. The minimum VCCO2 for power-on reset and configuration is 1.65V.
4. Termination resistance to a VCCO/2 level.
DS162 (v1.9) August 23, 2010
Advance Product Specification
www.xilinx.com
4
Page 4
Part Number XC6SLX9
Manufactur Xilinx
Description Spartan-6 FPGA
Total Page 70 Pages
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