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TPS51124 Datasheet

DUAL SYNCHRONOUS STEP-DOWN CONTROLLER


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TPS51124
SLVS616C – NOVEMBER 2005 – REVISED DECEMBER 2014
TPS51124 Dual Synchronous Step-Down Controller for Low-Voltage Power Rails
1 Features
1 High Efficiency, Low-Power Consumption,
Shutdowns to <1 μA
• Fixed Frequency Emulated On-Time Control,
Frequency Selectable From Three Options
• D-CAP™ Mode Enables Fast Transient Response
• Auto-Skip Mode
• Less Than 1% Initial Reference Accuracy
• Low Output Ripple
• Wide Input Voltage Range: 3 V to 28 V
• Output Voltage Range: 0.76 V to 5.5 V
• Low-Side RDS(ON) Loss-less Current Sensing
• Adaptive Gate Drivers With Integrated Boost
Diode
• Internal 1.2-ms Voltage-Servo Soft-Start
• Powergood Signals for Each Channel With Delay
Timer
• Output Discharge During Disable, Fault
2 Applications
Notebook I/O and Low-Voltage System Bus
3 Description
The TPS51124 is a dual, adaptive on-time D-CAP™
mode synchronous buck controller. The part enables
system designers to cost effectively complete the
suite of notebook power bus regulators with the
absolute lowest external component count and lowest
standby consumption. The fixed frequency emulated
adaptive on-time control supports seamless operation
between PWM mode at heavy load condition and
reduced frequency operation at light load for high
efficiency down to milliampere range. The main
control loop for the TPS51124 uses the D-CAP mode
that optimized for low ESR output capacitors such as
POSCAP or SP-CAP promises fast transient
response with no external compensation. Simple and
separate power good signals for each channel allow
flexibility of power sequencing. The part provides a
convenient and efficient operation with supply input
voltages (V5IN, V5FILT) ranging from 4.5 V to 5.5 V,
conversion voltages (drain voltage for the
synchronous high-side MOSFET) from 3 V to 28 V
and output voltages from 0.76 V to 5.5 V.
The TPS51124 is available in 24-pin VQFN package
specified from –40°C to 85°C ambient temperature
range.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS51124
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Input Voltage
3 V to 28 V
C9
22 µF
R5
R4 75 kΩ
73.2 kΩ
SGND
R2
75
kΩ
R1
28.7 kΩ
654321
VO2
1.5 V/10 A
SGND PGND
Power
Good2
C6
10 µF
Q3
IRF7821
L2
1 µH
EN2
C5
0.1 µF
7 PGOOD2
8 EN2
9 VBST2
10 DRVH2
TPS51124RGE
(QFN24)
PGOOD1 24
Power
Good1
EN1 23
EN1
VBST1 22
C2
0.1 µF
DRVH1 21
Q1
IRF7821
C4
2 x 330 µF
V5IN
4.5 V to 5.5 V
Q4
IRF8113
11 LL2
12 DRVL2
LL1 20
DRVL1 19
Q2
IRF8113
PGND
13 14
R6
6.8 kΩ
15 16 17
R7 R3
3.3Ω 6.8
kΩ
18
C7
4.7μF
C8
1μF
PGND
PGND
SGND
C3
L1 10 µF
1 µH
VO1
1.05 V/10 A
C1
2 x 330 µF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Page 1

TPS51124
SLVS616C – NOVEMBER 2005 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings .................................... 4
6.2 Recommended Operating Conditions...................... 4
6.3 Thermal Information .................................................. 4
6.4 Electrical Characteristics.......................................... 5
6.5 Typical Characteristics .............................................. 7
7 Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
8 Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1 Third-Party Products Disclaimer ........................... 20
11.2 Trademarks ........................................................... 20
11.3 Electrostatic Discharge Caution ............................ 20
11.4 Glossary ................................................................ 20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision B (September 2010) to Revision C
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision A (November 2005) to Revision B
Page
• Changed From: pin 48 = PGND1 To: pin 18 = PGND1 in the Pin Out illustration................................................................. 3
• Updated the Function Block Diagram................................................................................................................................... 10
Figure 19 - Removed the hysteretic symbol from the PWM component.............................................................................. 15
• Updated equation 9. Changed From: VOUT x 0.01 To: VOUT x 0.0132.................................................................................. 16
Changes from Original (November 2005) to Revision A
Page
• Updated the the circut illustration, Pin 21 changed From DRVL1 To: DRVH1 and Pin 19 changed From: DRVH1 to
DRVL1 .................................................................................................................................................................................... 1
• PG low hysteresis (PGOODx goes low) - deleted the Min -4% and Max -6% values ........................................................... 6
• PG high hysteresis (PGOODx goes low) - deleted the Min 4% and Max 6% values ............................................................ 6
• Hysteresis (recovery < 20 μs) - deleted the Min 8% and Max 12% values ........................................................................... 6
• Updated Figure 18, Pin 21 changed From DRVL1 To: DRVH1 and Pin 19 changed From: DRVH1 to DRVL1 ................. 14
2 Submit Documentation Feedback
Product Folder Links: TPS51124
Copyright © 2005–2014, Texas Instruments Incorporated
Page 2

www.ti.com
5 Pin Configuration and Functions
TPS51124
SLVS616C – NOVEMBER 2005 – REVISED DECEMBER 2014
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
VO1
VFB1
GND
TONSEL
VFB2
VO2
1
2
3
4
5
6
Thermal Pad
18 PGND1
17 TRIP1
16 V5IN
15 V5FILT
14 TRIP2
13 PGND2
PIN
NAME
NO.
DRVH1
21
DRVH2
10
DRVL1
19
DRVL2
12
EN1 23
EN2 8
GND
3
LL1 20
LL2 11
PGND1
18
PGND2
13
PGOOD1
24
PGOOD2
7
TONSEL
TRIP1
4
17
TRIP2
14
VBST1
22
VBST2
9
VFB1
VFB2
VO1
VO2
2
5
1
6
V5FILT
15
V5IN
16
Pin Functions
I/O DESCRIPTION
O
Synchronous high-side MOSFET driver outputs. LL node referenced floating drivers. The gate drive voltage
is defined by the voltage across VBST to LL node flying capacitor.
O
Synchronous low-side MOSFET driver outputs. PGND referenced drivers. The gate-drive voltage is defined
by V5IN voltage.
I Channel 1 and channel 2 enable pins. Connect to 5 V or 3.3 V to turn on SMPS
I Signal ground pin
I/O
Switch node connections for high-side drivers return. Also serve as input to current comparators and input
voltage monitor for on-time control circuitry.
I/O
Ground returns for DRVL1 and DRVL2. Also serve as input of current comparators. Connect PGND1,
PGND2, and GND strongly together near the IC. Output discharge current flows through this pin, also.
Power Good window comparator open drain output for channel 1 and 2. Pull up with a resistor to 5 V, or
O appropriate signal voltage. Current capability is 5 mA. PGOOD goes high 0.5 ms after VFB comes within
specified limits. Power bad, or the terminal goes low, is within 10 μs.
I On-time selection pin. See Table 1.
Overcurrent trip point set input. Connect resistor from this pin to GND to set threshold for synchronous low-
I side RDS(on) sense. Voltage across this pin and GND is compared to voltage across PGND and LL at over-
current comparator.
Supply input for synchronous high-side MOSFET driver (Boost Terminal). Connect capacitor from this pin
I to respective LL terminals. An internal PN diode is connected between V5IN to each of these pins. User
can add external Schottky diode if forward drop is critical to drive the MOSFET.
I SMPS voltage feedback inputs. Connect with feedback resistor divider.
I
Output connections to SMPS. These terminals serve two functions: On-time adjustment and output
discharge.
I
5-V power supply input for the entire control circuit except the MOSFET drivers. Connect RC low-pass filter
from V5IN to V5FILT.
I 5-V power supply input for FET gate drivers. Internally connected to VBSTx by PN diodes.
Copyright © 2005–2014, Texas Instruments Incorporated
Product Folder Links: TPS51124
Submit Documentation Feedback
3
Page 3

TPS51124
SLVS616C – NOVEMBER 2005 – REVISED DECEMBER 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VBST1, VBST2
Input voltage
VBST1, VBST2 (wrt LLx)
V5IN, V5FILT, EN1, EN2, VFB1, VFB2, TRIP1, TRIP2, VO1,
VO2, TONSEL
DRVH1, DRVH2
Output
voltage
DRVH1, DRVH2 (wrt LLx)
LL1, LL2
PGOOD1, PGOOD2, DRVL1, DRVL2
PGND1, PGND2
TA Operating ambient temperature
TJ Junction temperature
Tstg Storage temperature
MIN
–0.3
–0.3
–0.3
–1
–0.3
–2
–0.3
–0.3
–40
–40
–55
MAX
36
6
6
36
6
30
6
0.3
85
125
150
UNIT
V
V
°C
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted
6.2 Recommended Operating Conditions
over operating free-air temperature (unless otherwise noted)
Supply input voltage
V5IN, V5FILT
VBST1, VBST2
Input voltage
VBST1, VBST2 (wrt LLx)
EN1, EN2, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TONSEL
DRVH1, DRVH2
DRVH1, DRVH2 (wrt LLx)
Output voltage
LL1, LL2
PGOOD1, PGOOD2, DRVL1, DRVL2
PGND1, PGND2
TA Operating ambient temperature
MIN MAX UNIT
4.5 5.5 V
–0.1 34
–0.1 5.5 V
–0.1 5.5
–0.8 34
–0.1 5.5
–1.8 28 V
–0.1 5.5
–0.1 0.1
–40 85 °C
6.3 Thermal Information
THERMAL METRIC(1)
TPS51124
VQFN
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
42.9 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4 Submit Documentation Feedback
Product Folder Links: TPS51124
Copyright © 2005–2014, Texas Instruments Incorporated
Page 4
Part Number TPS51124
Manufactur Texas Instruments
Description DUAL SYNCHRONOUS STEP-DOWN CONTROLLER
Total Page 28 Pages
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