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Texas Instruments
Texas Instruments

TAS5122 Datasheet

30W STEREO DIGITAL AMPLIFIER POWER STAGE


TAS5122 Datasheet Preview


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TAS5122
SLES088D – AUGUST 2003 – REVISED MAY 2004
TM
30ĆW STEREO DIGITAL AMPLIFIER POWER STAGE
FEATURES
D 2 × 30 W (BTL) Into 6 at 1 kHz
D 95-dB Dynamic Range (in System With
TAS5026)
D < 0.2% THD+N (in System – 30 W RMS Into
6-Resistive Load)
D Device Power Efficiency Typical >90% Into
6-Load
D Self-Protection Design (Including
Undervoltage, Overtemperature, and Short
Conditions) With Error Reports
D Internal Gate Drive Supply Voltage Regulator
D EMI Compliant When Used With
Recommended System Design
THD + NOISE vs OUTPUT POWER
1
RL = 6
TC = 75°C
APPLICATIONS
D DVD Receiver
D Home Theatre
D Mini/Micro Component Systems
D Internet Music Appliance
DESCRIPTION
The TAS5122 is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-
speakers at up to 30 W per channel. The device
incorporates TI’s PurePath Digitalt technology and is
used with a digital audio PWM processor (TAS50XX) and
a simple passive demodulation filter to deliver high-quality,
high-efficiency, true-digital audio amplification.
The efficiency of this digital amplifier is typically greater
than 90%. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5122, safeguarding the device and speakers against
fault conditions that could damage the system.
THD + NOISE vs FREQUENCY
1
RL = 6
TC = 75°C
0.1
0.01
40m 100m
1 10
PO − Output Power − W
40
PO = 30 W
0.1
PO = 10 W
PO = 1 W
0.01
20
100 1k
f − Frequency − Hz
10k 20k
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
Page 1

TAS5122
SLES088D – AUGUST 2003 – REVISED MAY 2004
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5122 is offered in a thermally enhanced 56-pin
DCA package (thermal pad is on the bottom). Output of the
DCA package is highly dependent on thermal design. See
the Thermal Information section. Therefore, it is important
to design the heatsink carefully.
GND
GND
GREG
DVDD
GND
DGND
GND
PWM_AP
PWM_AM
RESET_AB
PWM_BM
PWM_BP
DREG
M1
M2
M3
DREG_RTN
PWM_CP
PWM_CM
RESET_CD
PWM_DM
PWM_DP
SD_AB
SD_CD
OTW
GREG
GND
GND
DCA PACKAGE
(TOP VIEW)
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
GND
GVDD
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND
GND
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND
GND
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD
GND
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TAS5122
DVDD to DGND
GVDD to GND
PVDD_X to GND (dc voltage)
OUT_X to GND (dc voltage)
BST_X to GND (dc voltage)
GREG to GND (2)
PWM_XP, RESET, M1, M2, M3, SD,
OTW
Maximum operating junction
temperature, TJ
Storage temperature
UNITS
–0.3 V to 4.2 V
28 V
28 V
28 V
40 V
14.2 V
–0.3 V to DVDD + 0.3 V
–40°C to 150°C
–40°C to 125°C
(1) Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-
maximum-ratedconditions for extended periods may affect device
reliability.
(2) GREG is treated as an input when the GREG pin is overdriven by
GVDD of 12 V.
ORDERING INFORMATION
TA
0°C to 70°C
PACKAGE
TAS5122DCA
DESCRIPTION
56-pin small TSSOP
PACKAGE DISSIPATION RATINGS
PACKAGE
RθJC
(°C/W)
RθJA
(°C/W)
56-pin DCA TSSOP
1.14 See Note 1
(1) The TAS5122 package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.
For this reason, RθJA a system parameter that characterizes the
thermal treatment provided in the application. An example and
discussion of typical system RθJA values are provided in the
Thermal Information section. This example provides additional
information regarding the power dissipation ratings. This example
should be used as a reference to calculate the heat dissipation
ratings for a specific application. TI application engineering
provides technical support to design heatsinks if needed.
2
Page 2

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TAS5122
SLES088D – AUGUST 2003 – REVISED MAY 2004
Terminal Functions
TERMINAL
NAME
NO.
FUNCTION(1)
DESCRIPTION
BST_A
54
P HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B
43
P HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C
42
P HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
31
P HS bootstrap supply (BST), external capacitor to OUT_D required
DGND 6 P Digital I/O reference ground
DREG 13 P Digital supply voltage regulator decoupling pin, capacitor connected to GND
DREG_RTN
17
P Digital supply voltage regulator decoupling return pin
DVDD 4 P I/O reference supply input (3.3 V)
GND
1, 2, 5,
P Power ground (I/O reference ground – pin 22)
7, 27, 28,
29, 36, 37,
48, 49, 56
GREG 3, 26 P Gate drive voltage regulator decoupling pin, capacitor to GND
GVDD
30, 55
P Voltage supply to on−chip gate drive and digital supply voltage regulators
M1 14 I Mode selection pin
M2 15 I Mode selection pin
M3 16 I Mode selection pin
OTW
25 O Overtemperature warning output, open drain with internal pullup
OUT_A
50, 51
O Output, half-bridge A
OUT_B
46, 47
O Output, half-bridge B
OUT_C
38, 39
O Output, half-bridge C
OUT_D
34, 35
O Output, half-bridge D
PVDD_A
52, 53
P Power supply input for half-bridge A
PVDD_B
44, 45
P Power supply input for half-bridge B
PVDD_C
40, 41
P Power supply input for half-bridge C
PVDD_D
32, 33
P Power supply input for half-bridge D
PWM_AM
9
I Input signal (negative), half-bridge A
PWM_AP
8
I Input signal (positive), half-bridge A
PWM_BM
11
I Input signal (negative), half-bridge B
PWM_BP
12
I Input signal (positive), half-bridge B
PWM_CM
19
I Input signal (negative), half-bridge C
PWM_CP
18
I Input signal (positive), half-bridge C
PWM_DM
21
I Input signal (negative), half-bridge D
PWM_DP
22
I Input signal (positive), half-bridge D
RESET_AB
10
I Reset signal, active low
RESET_CD
20
I Reset signal, active low
SD_AB
23
O Shutdown signal for half-bridges A and B
SD_CD
24
O
(1) I = input, O = output, P = power
Shutdown signal for half-bridges C and D
3
Page 3

TAS5122
SLES088D – AUGUST 2003 – REVISED MAY 2004
FUNCTIONAL BLOCK DIAGRAM
GREG
PWM_AP
RESET
PWM_BP
OTW
SD
PWM
Receiver
Timing
Control
Protection A
Protection B
GREG
PWM
Receiver
Timing
Control
To
Protection
Blocks
Gate
Drive
Gate
Drive
Gate
Drive
Gate
Drive
OT
Protection
UVP
GREG
DREG
DREG_RTN
GREG
PWM_CP
PWM
Receiver
Timing
Control
RESET
Protection C
Protection D
GREG
PWM_DP
PWM
Receiver
Timing
Control
Gate
Drive
Gate
Drive
Gate
Drive
Gate
Drive
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BST_A
PVDD_A
OUT_A
GND
BST_B
PVDD_B
OUT_B
GND
DREG
GVDD
GREG
GREG
DREG_RTN
BST_C
PVDD_C
OUT_C
GND
BST_D
PVDD_D
OUT_D
GND
4
Page 4
Part Number TAS5122
Manufactur Texas Instruments
Description 30W STEREO DIGITAL AMPLIFIER POWER STAGE
Total Page 20 Pages
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