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Mitel Networks Corporation
Mitel Networks Corporation

MT8815 Datasheet

ISO-CMOS 8 x 12 Analog Switch Array


MT8815 Datasheet Preview


ISO-CMOS MT8815
® 8 x 12 Analog Switch Array
Features
• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage: 4.5V to 13.2V
• 12Vpp analog signal capability
• RON 65max. @ VDD=12V, 25°C
RON 10@ VDD=12V, 25°C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumption ISO-CMOS technology
Applications
• Key systems
• PBX systems
• Mobile radio
• Test equipment /instrumentation
• Analog/digital multiplexers
• Audio/Video switching
ISSUE 1
November 1988
Ordering Information
MT8815AC 40 Pin Ceramic DIP
MT8815AE 40 Pin Plastic DIP
MT8815AP 44 Pin PLCC
-40° to 85°C
Description
The Mitel MT8815 is fabricated in MITEL’s ISO-
CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 12
array of crosspoint switches along with a 7 to 96 line
decoder and latch circuits. Any one of the 96
switches can be addressed by selecting the
appropriate seven address bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA input. VSS is the ground reference
of the digital inputs. The range of the analog signal
is from VDD to VEE.
STROBE
DATA RESET
VDD VEE
VSS
11
AX0
AX1
AX2
AX3
7 to 96
Decoder
Latches
AY0
8 x 12
Switch
Array
AY1
96 96
AY2
•••••••••••••••••••
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
Xi I/O
(i=0-11)
3-39
Page 1

MT8815 ISO-CMOS
Y3
AY2
RESET
AX3
AX0
NC
NC
X6
X7
X8
X9
X10
X11
NC
Y7
VSS
Y6
STROBE
Y5
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 NC
39 Y2
38 DATA
37 Y1
36 VDD
35 Y0
34 NC
33 X0
32 X1
31 X2
30 X3
29 X4
28 X5
27 NC
26 NC
25 AY1
24 AY0
23 AX2
22 AX1
21 Y4
6 5 4 3 2 1 44 43 42 41 40
NC 7
39 Y0
NC 8
38 NC
X6 9
37 X0
X7 10
36 X1
X8 11
35 X2
X9 12
X10 13
34 X3
33 X4
X11 14
32 X5
NC 15
31 NC
NC 16
30 NC
Y7 17
29 NC
18 19 20 21 22 23 24 25 26 27 28
40 PIN CERDIP/PLASTIC DIP
Pin Description
44 PIN PLCC
Figure 2 - Pin Connections
Pin #* Name
Description
1 Y3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.
2 AY2 Y2 Address Line (Input).
3 RESET Master RESET (Input): this is used to turn off all switches. Active High.
4,5 AX3,AX0 X3 and X0 Address Lines (Inputs): these are used to select X3 and X0 rows of switches.
6,7 NC No Connection.
8-13
X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch
array.
14 NC No Connection
15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
16 VSS Digital Ground Reference (Input).
17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
18 STROBE STROBE (Input): enables function selected by address and data. Address must be stable
before STROBE goes high and DATA must be stable on the falling edge of the STROBE.
Active High.
19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
20 VEE Negative Power Supply.
21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.
22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
26, 27
NC No Connection.
28 - 33
X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch
array.
34 NC No Connection.
35 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.
36 VDD Positive Power Supply.
37 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.
38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
39 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.
40 NC No Connection.
* Plastic DIP and CERDIP only.
3-40
Page 2

ISO-CMOS MT8815
Functional Description
Address Decode
The MT8815 is an analog switch matrix with an array
size of 8×12. The switch array is arranged such that
there are 8 columns by 12 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will interconnect any X I/O with any Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a 96
bit write only RAM in which the bits are selected by
the address inputs (AY0-AY2, AX0-AX3). Data is
presented to the memory on the DATA input. Data is
asynchronously written into memory whenever the
STROBE input is high and is latched on the falling
edge of STROBE. A logical “1” written into a
memory cell turns the corresponding crosspoint
switch on and a logical “0” turns the crosspoint off.
Only the crosspoint switches corresponding to the
addressed memory location are altered when data is
written into memory. The remaining switches retain
their previous states. Any combination of X and Y
inputs/outputs can be interconnected by establishing
appropriate patterns in the control memory. A logical
“1” on the RESET input will asynchronously return all
memory locations to logical “0” turning off all
crosspoint switches. Two voltage reference pins
(VSS and VEE) are provided for the MT8815 to
enable switching of negative analog signals. The
range for digital signals is from VDD to VSS while the
range for analog signals is from VDD to VEE. VSS
and VEE pins can be tied together if a single voltage
reference is needed.
The seven address inputs along with the STROBE
are logically ANDed to form an enable signal for the
resettable transparent latches. The DATA input is
buffered and is used as the input to all latches. To
write to a location, RESET must be low while the
address and data are set up. Then the STROBE
input is set high and then low causing the data to be
latched. The data can be changed while STROBE is
high, however, the corresponding switch will turn on
and off in accordance with the DATA input. DATA
must be stable on the falling edge of STROBE in
order for correct data to be written to the latch.
3-41
Page 3

MT8815 ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.
Parameter
Symbol
Min
Max Units
1 Supply Voltage
2 Analog Input Voltage
3 Digital Input Voltage
4 Current on any I/O Pin
VDD
VSS
VINA
VIN
I
-0.3
-0.3
-0.3
VSS-0.3
15.0
VDD+0.3
VDD+0.3
VDD+0.3
±15
V
V
V
V
mA
5 Storage Temperature
TS -65 +150
6 Package Power Dissipation
PLASTIC DIP
CERDIP
PD
PD
0.6
1.0
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
°C
W
W
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Characteristics
Sym Min Typ Max Units
Test Conditions
1 Operating Temperature
2 Supply Voltage
3 Analog Input Voltage
4 Digital Input Voltage
TO
VDD
VSS
VINA
VIN
-40
4.5
VEE
VEE
VSS
25 85
13.2
VDD-4.5
VDD
VDD
°C
V
V
V
V
DC Electrical Characteristics- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated.
Characteristics
Sym Min TypMax Units
Test Conditions
1 Quiescent Supply Current
IDD
2 Off-state Leakage Current
(See G.9 in Appendix)
IOFF
1 100 µA All digital inputs at VIN=VSS or
VDD
0.4 1.5 mA All digital inputs at VIN=2.4V +
VSS; VSS=7.0V
5 15 mA All digital inputs at VIN=3.4V
±1 ±500 nA IVXi - VYjI = VDD - VEE
See Appendix, Fig. A.1
3 Input Logic “0” level
VIL
0.8+VSS V VSS=7.5V; VEE=0V
4 Input Logic “1” level
VIH 2.0+VSS
V VSS=6.5V; VEE=0V
5 Input Logic “1” level
VIH 3.3
V
6 Input Leakage (digital pins) ILEAK
0.1 10
µA All digital inputs at VIN = VSS
or VDD
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics
Sym 25°C
70°C
85°C Units
Test Conditions
Typ Max Typ Max Typ Max
1 On-state VDD=12V RON 45 65 75 80
Resistance VDD=10V
55 75 85 90
VDD= 5V
120 185 215 225
(See G.1, G.2, G.3 in
Appendix)
2 Difference in on-state RON 5 10 10 10
resistance between two
switches
(See G.4 in Appendix)
VSS=VEE=0V,VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
VDD=12V, VSS=VEE=0,
VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
3-42
Page 4
Part Number MT8815
Manufactur Mitel Networks Corporation
Description ISO-CMOS 8 x 12 Analog Switch Array
Total Page 6 Pages
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