® 8 x 12 Analog Switch Array
• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage: 4.5V to 13.2V
• 12Vpp analog signal capability
• RON 65Ω max. @ VDD=12V, 25°C
• ∆RON ≤ 10Ω @ VDD=12V, 25°C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumption ISO-CMOS technology
• Key systems
• PBX systems
• Mobile radio
• Test equipment /instrumentation
• Analog/digital multiplexers
• Audio/Video switching
MT8815AC 40 Pin Ceramic DIP
MT8815AE 40 Pin Plastic DIP
MT8815AP 44 Pin PLCC
-40° to 85°C
The Mitel MT8815 is fabricated in MITEL’s ISO-
CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 12
array of crosspoint switches along with a 7 to 96 line
decoder and latch circuits. Any one of the 96
switches can be addressed by selecting the
appropriate seven address bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA input. VSS is the ground reference
of the digital inputs. The range of the analog signal
is from VDD to VEE.
7 to 96
8 x 12
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
40 PIN CERDIP/PLASTIC DIP
44 PIN PLCC
Figure 2 - Pin Connections
Pin #* Name
1 Y3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.
2 AY2 Y2 Address Line (Input).
3 RESET Master RESET (Input): this is used to turn off all switches. Active High.
4,5 AX3,AX0 X3 and X0 Address Lines (Inputs): these are used to select X3 and X0 rows of switches.
6,7 NC No Connection.
X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch
14 NC No Connection
15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
16 VSS Digital Ground Reference (Input).
17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
18 STROBE STROBE (Input): enables function selected by address and data. Address must be stable
before STROBE goes high and DATA must be stable on the falling edge of the STROBE.
19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
20 VEE Negative Power Supply.
21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.
22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
NC No Connection.
28 - 33
X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch
34 NC No Connection.
35 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.
36 VDD Positive Power Supply.
37 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.
38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
39 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.
40 NC No Connection.
* Plastic DIP and CERDIP only.
The MT8815 is an analog switch matrix with an array
size of 8×12. The switch array is arranged such that
there are 8 columns by 12 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will interconnect any X I/O with any Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a 96
bit write only RAM in which the bits are selected by
the address inputs (AY0-AY2, AX0-AX3). Data is
presented to the memory on the DATA input. Data is
asynchronously written into memory whenever the
STROBE input is high and is latched on the falling
edge of STROBE. A logical “1” written into a
memory cell turns the corresponding crosspoint
switch on and a logical “0” turns the crosspoint off.
Only the crosspoint switches corresponding to the
addressed memory location are altered when data is
written into memory. The remaining switches retain
their previous states. Any combination of X and Y
inputs/outputs can be interconnected by establishing
appropriate patterns in the control memory. A logical
“1” on the RESET input will asynchronously return all
memory locations to logical “0” turning off all
crosspoint switches. Two voltage reference pins
(VSS and VEE) are provided for the MT8815 to
enable switching of negative analog signals. The
range for digital signals is from VDD to VSS while the
range for analog signals is from VDD to VEE. VSS
and VEE pins can be tied together if a single voltage
reference is needed.
The seven address inputs along with the STROBE
are logically ANDed to form an enable signal for the
resettable transparent latches. The DATA input is
buffered and is used as the input to all latches. To
write to a location, RESET must be low while the
address and data are set up. Then the STROBE
input is set high and then low causing the data to be
latched. The data can be changed while STROBE is
high, however, the corresponding switch will turn on
and off in accordance with the DATA input. DATA
must be stable on the falling edge of STROBE in
order for correct data to be written to the latch.
Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.
1 Supply Voltage
2 Analog Input Voltage
3 Digital Input Voltage
4 Current on any I/O Pin
5 Storage Temperature
TS -65 +150
6 Package Power Dissipation
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Sym Min Typ Max Units
1 Operating Temperature
2 Supply Voltage
3 Analog Input Voltage
4 Digital Input Voltage
DC Electrical Characteristics†- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated.
Sym Min Typ‡ Max Units
1 Quiescent Supply Current
2 Off-state Leakage Current
(See G.9 in Appendix)
1 100 µA All digital inputs at VIN=VSS or
0.4 1.5 mA All digital inputs at VIN=2.4V +
5 15 mA All digital inputs at VIN=3.4V
±1 ±500 nA IVXi - VYjI = VDD - VEE
See Appendix, Fig. A.1
3 Input Logic “0” level
0.8+VSS V VSS=7.5V; VEE=0V
4 Input Logic “1” level
V VSS=6.5V; VEE=0V
5 Input Logic “1” level
6 Input Leakage (digital pins) ILEAK
µA All digital inputs at VIN = VSS
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Typ Max Typ Max Typ Max
1 On-state VDD=12V RON 45 65 75 80
55 75 85 90
120 185 215 225
(See G.1, G.2, G.3 in
2 Difference in on-state ∆RON 5 10 10 10
resistance between two
(See G.4 in Appendix)
Ω IVXi-VYjI = 0.4V
Ω See Appendix, Fig. A.2
Ω VDD=12V, VSS=VEE=0,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
webmaste! click here