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MPS

MP1048 Datasheet

Full Bridge CCFL Controller


MP1048 Datasheet Preview


www.DataSheet.co.kr
The Future of Analog IC Technology
MP1048
Full Bridge
CCFL Controller
DESCRIPTION
The MP1048 is a fixed operating frequency
inverter controller that controls four external
N-Channel power MOSFETs in a full-bridge
configuration. The inverter is designed to power
up to 6 cold cathode fluorescent lamps (CCFLs)
to backlight liquid crystal displays. Its full-bridge
architecture converts unregulated DC input
voltages to the nearly pure sine waves required
to ignite and operate CCFLs.
For reliable lamp ignition, the operating
frequency is set by an external resistor and
during startup is temporarily swept toward the
unloaded resonant frequency of the tank. Burst
mode or analog mode dimming are controlled
with an external analog signal. Built-in fault
management features include an open lamp
regulator, a transformer secondary peak current
regulator and a dual-mode fault timer. The
secondary over-current timeout can be
shortened with external components. The
MP1048 is available in TSSOP28 and SOIC28
packages.
TYPICAL APPLICATION
FEATURES
Capable of Driving up to 6 Lamps
Controls Four External, Low Cost, N-Channel
MOSFETs
Fixed Operating Frequency
Input Voltage Range of 10V to 22V
Lamp Current and Voltage Regulation
Full-Wave Sense Amp
Analog and Burst Mode Dimming Control
Integrated Burst Mode Oscillator and Modulator
Soft-On and Soft-Off Burst Envelope
Open Lamp Protection
Secondary Over-Current Protection
Dual-Mode Fault Timer
Available in TSSOP28 and SOIC28 Packages
APPLICATIONS
Desktop LCD Flat Panel Displays
Monitors
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The MP1048 is covered by US Patents 6,683,422, 6,316,881, and 6,114,814.
Other Patents Pending.
DBRT
ABRT
EN
1
SI
2
LI
3
LV
4
COMP
5
AG
6
FT
7
LCS
8
LCC
9
BRC
10
BRS
11
DBRT
12
ABRT
13
EN
14
NC
PGL
LGL
VCCL
OUTL
UGL
BTL
PRL
PGR
LGR
VCCR
OUTR
UGR
BTR
PRR
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
VPS
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
1
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PACKAGE REFERENCE
TOP VIEW
SI 1
LI 2
LV 3
COMP 4
AG 5
FT 6
LCS 7
LCC 8
BRC 9
BRS 10
DBRT 11
ABRT 12
EN 13
N/C 14
28 PGL
27 LGL
26 VCCL
25 OUTL
24 UGL
23 BTL
22 PRL
21 PGR
20 LGR
19 VCCR
18 OUTR
17 UGR
16 BTR
15 PRR
Part Number* Package
Temperature
MP1048EM
TSSOP28 –20°C to +85°C
MP1048EY
SOIC28
–20°C to +85°C
*
For
For
Tape & Reel, add suffix –Z (eg. MP1048EM–Z)
RoHS Compliant Packaging, add suffix –LF
(eg. MP1048EM–LF–Z)
MP1048 – FULL BRIDGE CCFL CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
Input Voltage VPRR, VPRL ............................... 24V
Logic Inputs ................................ –0.3V to +6.5V
Inputs SI, LI, LV ................................ –5V to +5V
Junction Temperature...............................150°C
Power Dissipation...................................... 0.6W
Junction Temperature...............................150°C
Lead Temperature (Solder) ......................260°C
Operating Frequency............................. 150KHz
Storage Temperature ..............–55°C to +150°C
Recommended Operating Conditions (2)
Input Voltage VPRR, VPRL .................... 10V to 22V
Analog Brightness Voltage VABRT....... 0V to 1.2V
Digital Brightness Voltage VDBRT........ 0V to 1.2V
Enable Voltage VEN............................ 0V to 5.0V
Operating Frequency............. 20KHz to 100KHz
Operating Frequency (Typical) ................ 60KHz
Operating Temperature .............–20°C to +85°C
Thermal Resistance (3) θJA θJC
TSSOP28 ............................... 82 ...... 20... °C/W
SOIC28................................... 60 ...... 30... °C/W
Notes:
1) The device is not guaranteed to function outside of its
operating conditions.
2) Exceeding these ratings may damage the device.
3) Measured on approximately 1” square of 1 oz copper.
ELECTRICAL CHARACTERISTICS
VPRR = VPRL = 17.5V, VBRC = VLCC = GND, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min Typ
Output
Gate Pull-Down
Gate Pull-Up
Damper On Resistance
EN
Threshold
Hysteresis
Sync Timing
DBRT Logic Input Threshold
DBRT Logic Input Hysteresis
Burst Rate Generator
Source Current
Lower Threshold
Upper Threshold
RGD
RGU
RON
VTH
VTH_HYS
VTH
VTH_HYS
VBRS = VCC
VBRS = VCC
ISRC(BRS)
VV(BRS)
VP(BRS)
VBRS = 2V
2.0
20
1.2
1.2
0.3
1.8 2.0
0.2
125 150
2.2 2.35
3.2 3.4
Max Units
k
2.0 V
V
2.3 V
V
175 µA
2.5 V
3.6 V
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
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MP1048 – FULL BRIDGE CCFL CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VPRR = VPRL = 17.5V, VBRC = VLCC = GND, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min Typ
Supply Current
Supply Current (Enabled)
Supply Current (Disabled)
Operating Frequency
Accuracy of f0
Frequency Set Voltage
Lamp Current Feedback
Magnitude
Accuracy
Input Resistance
Open Lamp Voltage Feedback
Threshold (Peak)
Secondary Peak Current
Threshold
IPR
IPR
f0 R3 = 100k
VLCS
|VLI|
VLI
RLI
VTH(LV)
VABRT > 1.2V
VABRT = 0V
VLI < 0V
VTH(SI)
2.2
3
45 49
3
1.13 1.18
1.134
0.35
1.15
1.15
1.20
0.40
3
60
1.20
1.20
Fault Timer
Threshold
Sink Current
Open Lamp Source Current
Secondary Over-Current Source
Current
Vt(FT)
ISINK(FT)
ISO(FT)+
ISP(FT)+
1.15 1.20
1
1
65
Comp
Clamp Voltage
Reference Current
Decay Current
Output (VCCR and VCCL)
Voltage
Current
VCOMP
ICOMP+
ICOMP-
End of Burst
VCC
ICC
0.62
20
20
5.7 6.0
5
Max Units
3 mA
25 µA
53 KHz
8%
1.23 V
1.266
0.45
1.25
1.25
V
%
k
V
V
1.25
V
µA
µA
µA
V
µA
µA
6.3 V
mA
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
3
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MP1048 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS
Pin # Name Description
1 SI Secondary Current Feedback Input. Connect a current sense resistor from the cold end of the
secondary winding to ground. Connect this pin to the junction of the resistor and the secondary
winding. If the voltage at SI exceeds +1.2V, a pulse of current will pull down on the COMP pin in
an attempt to regulate the secondary current and the Fault Timer will be started.
2 LI Lamp Current Feedback Input. Connect this pin to the cold end of the lamp and shunt a sense
resistor to ground. The sense amplifier will sink a current from the COMP pin that is proportional
to the absolute value of the voltage at this pin. (In regulation the average of the absolute value of
the voltage at this pin is determined by the voltage at the ABRT pin).
3 LV Lamp Voltage Feedback Input. Connect a capacitive voltage divider from the hot end of the lamp
to ground. Connect this pin to the tap on the divider and shunt a bias resistor to ground. If the
voltage at LV exceeds +1.2V, a pulse of current will pull down on the COMP pin to attempt to
regulate the lamp voltage and the Fault Timer will be started.
4 COMP Feedback Compensation Node. Connect a compensation capacitor from this pin to ground.
5 AG Analog Ground.
6 FT Fault Timing. Connect a timing capacitor from this pin to AG to set the fault timeout period.
7 LCS Lamp Operating Clock Set. Connect a resistor from this pin to AG. This resistor sets the
operating frequency of the MP1048.
8 LCC Lamp Clock Control. LCC provides compensation when the operating clock is swept in order to
strike the lamp. Connect a resistor in series with a capacitor from LCC to AG. Connect a smaller
capacitor directly from LCC to AG. Connect only a single capacitor to AG, if some sweeping of
the operating clock can be tolerated during open lamp conditions. Connect LCC to AG to force
the operating clock to the selected value at all times.
9 BRC Burst Repetition Rate Control. Connect BRC to AG.
10 BRS Burst Repetition Rate Setting. If the burst repetition rate is to be synchronized to an external
clock, connect a capacitor from BRS to AG. If the burst rate generator is free-run and will not be
synchronized with an external clock, connect a resistor in parallel with a capacitor from BRS to
AG. If the burst is to be controlled by an external logic signal, connect BRS to VCC and apply the
logic signal to the DBRT pin.
11 DBRT Burst-Mode (Digital) Brightness Control Input. The voltage range of 0V to 1.2V at DBRT linearly
sets the burst-mode duty cycle from minimum 10% to 100%. If burst dimming is not used, tie
DBRT to VCC.
12 ABRT Analog Brightness Control Input. The voltage range of 0V to 1.2V at ABRT sets the 3:1 dimming
range for the lamp current. If analog dimming is not used, tie ABRT to VCC.
13 EN Enable Input. Pull EN high to turn on the MP1048; low to turn it off.
14 NC No Connect.
15 PRR Input Power Rail, Right-Side. Connect PRR directly to the drain of the high-side, right-side,
external power MOSFET.
16 BTR Output Bootstrap, Right-Side. BTR provides gate bias for the right-side high-side MOSFET.
Connect a capacitor from BTR to OUTR.
17 UGR High-Side MOSFET Gate Output, Right-Side. Connect UGR to the gate of the high-side,
right-side, external power MOSFET.
18 OUTR Bridge Output, Right-Side. Connect OUTR to the source of the right-side, high-side
MOSFET and the drain of the low-side, right-side MOSFET.
19 VCCR Voltage Rail Output, Right-Side. VCCR allows bypassing the bias supply for the control
circuitry. Bypass VCCR with a 0.47µF capacitor. Connect to VCCL.
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
4
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Page 4
Part Number MP1048
Manufactur MPS
Description Full Bridge CCFL Controller
Total Page 12 Pages
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