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ON Semiconductor
ON Semiconductor

MC14040BCP Datasheet

12-Bit Binary Counter


MC14040BCP Datasheet Preview


MC14040B
12-Bit Binary Counter
The MC14040B 12–stage binary counter is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple–carry binary counter. The device
advances the count on the negative–going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency–driving circuits.
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Common Reset Line
Pin–for–Pin Replacement for CD4040B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14040BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14040B
AWLYWW
1
16
TSSOP–16
DT SUFFIX
CASE 948F
14
040B
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14040B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14040BCP
PDIP–16
2000/Box
MC14040BD
SOIC–16
2400/Box
MC14040BDR2 SOIC–16 2500/Tape & Reel
MC14040BDT
TSSOP–16
96/Rail
MC14040BF
SOEIAJ–16 See Note 1.
MC14040BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14040B/D
Page 1

CLOCK
10
RESET
11
MC14040B
PIN ASSIGNMENT
Q12 1
Q6 2
Q5 3
Q7 4
Q4 5
Q3 6
Q2 7
VSS 8
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 R
10 C
9 Q1
TRUTH TABLE
Clock
X
Reset
0
0
1
Output State
No Change
Advance to next state
All Outputs are low
X = Don’t Care
LOGIC DIAGRAM
Q1 Q2 Q3
9 76
CQ
CQ
CQ
CQ
R
CQ
R
CQ
R
Q10
14
Q11
15
Q12
1
CQ
CQ
CQ
CQ
R
CQ
R
C
R
Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2
Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12
VDD = PIN 16
VSS = PIN 8
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Page 2

MC14040B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
VDD – 55_C
25_C
125_C
Symbol Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin= VDDor0
“0” Level VOL
5.0
10
15
— 0.05 —
— 0.05 —
— 0.05 —
0 0.05 — 0.05
0 0.05 — 0.05
0 0.05 — 0.05
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = 0 or VDD
“1” Level VOH
5.0 4.95 — 4.95
10 9.95 — 9.95
15 14.95 — 14.95
5.0
10
15
— 4.95 —
— 9.95 —
— 14.95 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage
“0” Level VIL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 4.5 or 0.5 Vdc)
5.0 — 1.5 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 9.0 or 1.0 Vdc)
10 — 3.0 —
(VO = 13.5 or 1.5 Vdc)
15 — 4.0 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΓ1”Level VIH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 0.5 or 4.5 Vdc)
5.0 3.5 — 3.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 1.0 or 9.0 Vdc)
10 7.0 — 7.0
(VO = 1.5 or 13.5 Vdc)
15 11 — 11
2.25
4.50
6.75
2.75
5.50
8.25
1.5 — 1.5
3.0 — 3.0
4.0 — 4.0
— 3.5 —
— 7.0 —
— 11 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 2.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 13.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 0.4 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Vin = 0)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current
(Per Package)
Source
IOH
Sink IOL
Iin
Cin
IDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Dynamic plus Quiescent,
Per Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(CL = 50 pF on all outputs, all
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎbuffers switching)
IT
5.0 – 3.0 — – 2.4 – 4.2
5.0 – 0.64 — – 0.51 – 0.88
10 – 1.6 — – 1.3 – 2.25
15 – 4.2 — – 3.4 – 8.8
— – 1.7 —
— – 0.36 —
— – 0.9 —
— – 2.4 —
5.0 0.64 — 0.51 0.88
10 1.6 — 1.3 2.25
15 4.2 — 3.4
8.8
— 0.36 —
— 0.9 —
— 2.4 —
15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0
————
5.0
7.5 —
5.0
5.0
0.005
5.0
150
10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
5.0 IT = (0.42 µA/kHz) f + IDD
10 IT = (0.85 µA/kHz) f + IDD
15 IT = (1.43 µA/kHz) f + IDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
µAdc
pF
µAdc
µAdc
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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Page 3

MC14040B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTTLH, TTHL = (1.5 ns/pF) CL + 25 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns
TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock to Q1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL, tPLH = (1.7 ns/pF) CL + 315 ns
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL, tPLH = (0.5 ns/pF) CL + 95 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock to Q12
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL, tPLH = (1.7 ns/pF) CL + 2415 ns
tPHL, tPLH = (0.66 ns/pF) CL + 867 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL, tPLH = (0.5 ns/pF) CL + 475 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time
Reset to Qn
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL = (1.7 ns/pF) CL + 485 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL = (0.86 ns/pF) CL + 182 ns
tPHL = (0.5 ns/pF) CL + 145 ns
Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Width
Symbol
tTLH,
tTHL
tPLH,
tPHL
tPHL
tWH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequency
fcl
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Rise and Fall Time
tTLH, tTHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Width
tWH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Removal Time
trem
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. Theformulasgivenareforthetypicalcharacteristicsonlyat25_C.
VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
Min Typ (8.) Max Unit
ns
— 100 200
— 50 100
— 40 80
ns
— 260 520
— 115 230
— 80 160
ns
1625
3250
— 720 1440
— 500 1000
ns
— 370 740
— 155 310
— 115 230
385 140
150 55
115 38
— ns
— 2.1 1.5 MHz
— 7.0 3.5
— 10.0 4.5
No Limit
ns
960 320
360 120
270 80
130 65
50 25
30 15
— ns
— ns
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
500 µF
VDD
ID
0.01 µF
CERAMIC
PULSE
GENERATOR
C Q1
Q2
R Qn
VSS
CL
CL
CL
CLOCK
20 ns
90%
50%
10%
50% DUTY CYCLE
20 ns
VDD
VSS
Figure 1. Power Dissipation Test Circuit
and Waveform
PULSE
GENERATOR
VDD
C Q1
Q2
R Qn
VSS
CL
CL
CL
CLOCK
Q
20 ns
tPLH
90%
50%
10%
tTLH
90%
50%
10%
tWH
tTHL
20 ns
tPHL
Figure 2. Switching Time Test Circuit
and Waveforms
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4
Page 4
Part Number MC14040BCP
Manufactur ON Semiconductor
Description 12-Bit Binary Counter
Total Page 8 Pages
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MC14040BCP datasheet
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