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Lattice Semiconductor
Lattice Semiconductor

LFXP Datasheet

LatticeXP Family


LFXP Datasheet Preview


www.DataSheeLt4Ua.ctotmiceXP Family Data Sheet
DS1001 Version 05.1, November 2007
Page 1

LatticeXP Family Data Sheet
Introduction
July 2007
Features
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• No external configuration memory
• Excellent design security, no bit stream to
intercept
• Reconfigure SRAM based logic in milliseconds
www.DataSheet4U.comSRAM and non-volatile memory programmable
through system configuration and JTAG ports
Sleep Mode
• Allows up to 1000x static current reduction
TransFR™ Reconfiguration (TFR)
• In-field logic update while system operates
Extensive Density and Package Options
• 3.1K to 19.7K LUT4s
• 62 to 340 I/Os
• Density migration supported
Embedded and Distributed Memory
• 54 Kbits to 396 Kbits sysMEM™ Embedded
Block RAM
• Up to 79 Kbits distributed RAM
• Flexible memory resources:
Distributed and block memory
Data Sheet DS1001
Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
– SSTL 18 Class I
SSTL 3/2 Class I, II
– HSTL15 Class I, III
HSTL 18 Class I, II, III
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
Dedicated DDR Memory Support
• Implements interface up to DDR333 (166MHz)
sysCLOCK™ PLLs
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shifting
System Level Support
• IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer capability
• Onboard oscillator for configuration
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
Table 1-1. LatticeXP Family Selection Guide
Device
LFXP3
LFXP6
PFU/PFF Rows
16 24
PFU/PFF Columns
24 30
PFU/PFF (Total)
384 720
LUTs (K)
36
Distributed RAM (KBits)
12
23
EBR SRAM (KBits)
54 72
EBR SRAM Blocks
68
VCC Voltage
PLLs
1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V
22
Max. I/O
136 188
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
62
144-pin TQFP (20 x 20 mm)
100
100
208-pin PQFP (28 x 28 mm)
136
142
256-ball fpBGA (17 x 17 mm)
188
388-ball fpBGA (23 x 23 mm)
484-ball fpBGA (23 x 23 mm)
LFXP10
32
38
1216
10
39
216
24
1.2/1.8/2.5/3.3V
4
244
188
244
LFXP15
40
48
1932
15
61
324
36
1.2/1.8/2.5/3.3V
4
300
188
268
300
LFXP20
44
56
2464
20
79
396
44
1.2/1.8/2.5/3.3V
4
340
188
268
340
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1 DS1001 Introduction_01.5a July 6, 2007 3:01 p.m.
Page 2

Lattice Semiconductor
Introduction
LatticeXP Family Data Sheet
Introduction
The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a
single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs.
The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-
ogy. With this technology, expensive external configuration memories are not required and designs are secured
from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.
The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-
www.DataSheeat4nUn.cootamtes it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-2
Page 3

LatticeXP Family Data Sheet
Architecture
July 2007
Data Sheet DS1001
Architecture Overview
The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 2-
1.
On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In configuration mode this non-
volatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up,
www.DataSheetth4eU.ccoomnfiguration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this
technology, expensive external configuration memories are not required and designs are secured from unautho-
rized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in
microseconds, providing an “instant-on” capability that allows easy interfacing in many applications.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeXP architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG
port which allows for serial or parallel device configuration. The LatticeXP devices are available for operation from
3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1 DS1001 Architecture_02.0 July 6, 2007 3:03 p.m.
Page 4
Part Number LFXP
Manufactur Lattice Semiconductor
Description LatticeXP Family
Total Page 30 Pages
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