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Hynix Semiconductor
Hynix Semiconductor

HY5DU561622CT Datasheet

(HY5DU56xx22CT) 256M-P DDR SDRAM


HY5DU561622CT Datasheet Preview


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HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
HY5DU561622CT-D4/D43
256M-P DDR SDRAM
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
HY5DU561622CT-D4/D43
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Oct. 2003
Page 1

DESCRIPTION
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
HY5DU561622CT-D4/D43
PRELIMINARY
The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Syn-
chronous DRAM, ideally suited for the main memory applications which requires large memory density and high band-
width.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD/VDDQ = 2.5 ~ 2.7V
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
ORDERING INFORMATION
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• CAS latency 3 supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed
/RAS
• tRAS Lock-out function supported
• Auto refresh and Self refresh supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
• Full and Half strength driver option controlled by
EMRS
OPERATING FREQUENCY
Part No.
HY5DU56422CT-D*
HY5DU56822CT-D*
HY5DU561622CT-D*
Configuration
64Mx4
32Mx8
16Mx16
Package
400mil
66pin
TSOP-II
Grade
- D4
- D43
Speed
200MHz
200MHz
Remark
(CL-tRCD-tRP)
DDR400 (3-4-4)
DDR400 (3-3-3)
* Note : D of speed indicates DDR400.
Rev. 0.3 / Oct. 2003
3
Page 2

PIN CONFIGURATION
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
HY5DU561622CT-D4/D43
x4
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x8 x16
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
DNU
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 400mil X 875mil 52
16
17
66pin TSOP -II
51
50
18 0.65mm pin pitch 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
x16
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x4
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
ROW AND COLUMN ADDRESS TABLE
ITEMS
Organization
Row Address
Column Address
Bank Address
Auto Precharge Flag
Refresh
64Mx4
16M x 4 x 4banks
A0 - A12
A0-A9, A11
BA0, BA1
A10
8K
32Mx8
8M x 8 x 4banks
A0 - A12
A0-A9
BA0, BA1
A10
8K
16Mx16
4M x 16 x 4banks
A0 - A12
A0-A8
BA0, BA1
A10
8K
Rev. 0.3 / Oct. 2003
3
Page 3
Part Number HY5DU561622CT
Manufactur Hynix Semiconductor
Description (HY5DU56xx22CT) 256M-P DDR SDRAM
Total Page 34 Pages
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