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NXP
NXP

HEF4094BP Datasheet

8-stage shift-and-store bus register


HEF4094BP Datasheet Preview


INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4094B
MSI
8-stage shift-and-store bus register
Product specification
File under Integrated Circuits, IC04
January 1995
Page 1

Philips Semiconductors
8-stage shift-and-store bus register
Product specification
HEF4094B
MSI
DESCRIPTION
The HEF4094B is an 8-stage serial shift register having a
storage latch associated with each stage for strobing data
from the serial input to parallel buffered 3-state outputs
O0 to O7. The parallel outputs may be connected directly
to common bus lines. Data is shifted on positive-going
clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR)
input is HIGH. Data in the storage register appears at the
outputs whenever the output enable (EO) signal is HIGH.
Two serial outputs (Os and O’s) are available for cascading
a number of HEF4094B devices. Data is available at Os on
positive-going clock edges to allow high-speed operation
in cascaded systems in which the clock rise time is fast.
The same serial information is available at O’s on the next
negative-going clock edge and provides cascading
HEF4094B devices when the clock rise time is slow.
Fig.1 Functional diagram.
January 1995
Fig.2 Pinning diagram.
HEF4094BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4094BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4094BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
D
CP
STR
data input
clock input
strobe input
EO
Os, O’s
O0 to O7
output enable input
serial outputs
parallel outputs
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
2
Page 2

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Fig.3 Logic diagram.
Fig.4 One D-latch.
Page 3

Philips Semiconductors
8-stage shift-and-store bus register
FUNCTION TABLE
INPUTS
CP EO STR
LX
LX
HL
HH
HH
HH
PARALLEL OUTPUTS
D O0
XZ
On
Z
XZ
Z
X nc
nc
LL
HH
H nc
On-1
On-1
nc
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. = positive-going transition
5. = negative-going transition
6. Z = high impedance off state
7. nc = no change
8. O’6 = the information in the seventh shift register stage
SERIAL OUTPUTS
Os O’s
O’6 nc
nc O7
O’6 nc
O’6 nc
O’6 nc
nc O7
Product specification
HEF4094B
MSI
At the positive clock edge the information in the 7th register stage is transferred to the 8th register stage and the
Os output.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times 20 ns
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5 2100 fi + ∑ (foCL) × VDD2
10 9700 fi + ∑ (foCL) × VDD2
15 26 000 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
Page 4
Part Number HEF4094BP
Manufactur NXP
Description 8-stage shift-and-store bus register
Total Page 7 Pages
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Related Datasheet

HEF4094B , HEF4094BD , HEF4094BF , HEF4094BN , HEF4094BP , HEF4094BT ,

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