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Semico

CS9370 Datasheet

DTMF Receiver


CS9370 Datasheet Preview


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Semic
CS9370
DTMF Receiver
The Document is Applied to: CS9370DGPCS9370DGO
General Description
The CS9370 is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The
filter section uses switched capacitor techniques for high-and low-group filters and dial-tone rejection. Digital counting
techniques are employed in the decoder to detect and decode all 16 DTMF tone-pairs into 4-bit code. External
component count is minimized by on-chip provision of a differential input amplifier, clock-oscillator and latched 3-state
bus interface.
Features
z CMOS, 5/3 Volt operation.
z Excellent performance with minimum board quality.
z Central office quality.
z Low power consumption.
z Power-Down mode
z Inhibit-mode
z Package: DIP18, SOP18
Absolute Maximum Ratings
Supply Voltage........................................-0.3+6.0V
Operating Temperature...........................-40+85
Storage Temperature............................-65+150
Power Dissipation............................................ 35mW
Pin Configuration
IN+ 1
IN- 2
GS 3
VREF 4
INH 5
PWDN 6
OSC1 7
OSC2 8
VSS 9
18 VDD
17 St/GT
16 ESt
15 StD
14 Q4
13 Q3
12 Q2
11 Q1
10 TOE
DC Electrical Characteristics (Unless otherwise specified: Ta=25)
Parameter
Description
Test Condition
SUPPLY:
VDD
ICC
PO
IS
INPUTS:
Operating supply voltage
Operating supply current
Power consumption
Standby current
F=3.579MHzVDD=5V
VPWDN=VDD
VIL Low level input voltage
VIH High level input voltage
IIH/IIL Input leakage current
VIN=VSS or VDD
ISO Pull up (source) current
TOEPin 10=0V
RIN
Input Signal Impedance (Inputs 1,
2)
@1kHz
VTST
OUTPUT:
VOL
VOH
IOL
IOH
VREF
ROR
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output High (source) current
Output voltage
Output resistance
No load
No load
VOUT =0.4V
VOUT =4.6V
No load
Min. Typ. Max.
2.5 5.5
3.0 7
15 35
100
1.5
3.5
0.1
7.5 15
10
2.35
0.03
4.97
1.0 2.5
0.4 0.8
2.4 2.7
10
Unit
V
mA
mW
μA
V
V
μA
μA
MΩ
V
V
V
mA
mA
V
kΩ
Vol: 2006-01-E
2006-02-27
1/4
Datasheet pdf - http://www.DataSheet4U.net/
Page 1

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CS9370
Operating Characteristics
Gain Setting Amplifier
Parameter
Description
IIN Input leakage current
RIN Input resistance
VOS
PSRR
Input offset voltage
Power supply rejection
CMRR
Common mode rejection
AVOL DC open loop voltage gain
FC Open loop unity gain bandwidth
VD Output voltage swing
CL Tolerable capacitive load (GS)
RL Tolerable resistive load (GS)
VCM Common mode range
Test Condition
VSS<VIN<VDD
1kHz
-3.0<VIN<3.0
RL100kΩ to VSS
No load
Typ.
±100
10
±25
60
60
65
1.5
4.5
100
50
3.0
Unit
nA
MΩ
mV
dB
dB
dB
MHz
VPP
pF
kΩ
VPP
AC Characteristics
Parameter
Description
Min.
Valid input signal
level
(each tone signal)
Twist accept limit
Min
Max
Positive
Negative
+1
883
Freq. deviation accept limit
Freq. deviation reject limit
±3.5%
Third tone tolerance
Noise tolerance
Dial tone tolerance
TIMING:
tDP
tDA
tREC
tREC
tID
tDO
OUTPUTS:
Tone present detection time
Tone absent detection time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
5
0.5
20
20
tPQ Propagation delay (St to Q)
tPSED Propagation delay (St to StD)
tQSED Output data se up (Q to Std)
tPTE
tPTD
CLOCK:
Propagation ENABLE
Delay (TOE to Q) DISABLE
fCLK
Crystal/Clock frequency
3.5759
CLO
Clock output (OSC2) Capacitive
Load
Notes:
1. dBm = decibels above or below a reference power of
1mW into a 600Ω load.
2. Digit sequences consist of all 16 DTMF tones.
3. Tone duration = 40ms, Tone pause = 40ms
Typ. Max. Unit
-40 dBm
7.75 mVRMS
dBm
mVRMS
10 dB
10 dB
±1.5%
±2Hz
Nom.
Nom.
-16
-12 dB
+18 dB
14 16 ms
4 8.5 ms
40 ms
ms
40 ms
ms
8 11 μs
12 μs
4.5 μs
50 60 ns
300 ns
3.5795
3.581
30
MHz
pf
Note
1,2,3,5,6,9,11
1,2,3,5,6,9,11
1,2,3,5,6,9,11
1,2,3,5,6,9,11
2,3,6,9,11
2,3,5,9,11
2,3,5,11
2,3,4,5,9,10,11
2,3,4,5,7,9,10,11
2,3,4,5,8,9,10,11
(User adjustable)
(User adjustable)
(User adjustable)
TOE=VDD
RL=10kΩ
CL=50pf
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have an equal
amplitude.
6. Tone pair is deviated by ±1.5% ±2Hz.
2/4
Datasheet pdf - http://www.DataSheet4U.net/
Page 2

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CS9370
7. Bandwidth limited (3kHz) Gaussian Noise.
8. The precise dial tone frequencies are (350Hz and
440Hz) ±2%.
9. For an error rate of less than 1 in 10,000.
10. Reference to the lowest level frequency component
in DTMF signal.
11. Added a 0.1μf capacitor between VDD and VSS.
Pin Description
Pin Sym. I/O
1 IN+ I
2 IN- I
3 GS O
4 VREE O
5 INH I
6 PWDN I
7 OSC1 I
8 OSC2 O
9 VSS
10 TOE I
1114 Q1Q4 O
15 StD O
16 Est O
17 St/GT I/O
18 VDD
Port
-
-
-
-
CMOS IN
pull down
CMOS IN
pull down
-
-
-
CMOS IN
pull up
-
CMOS OUT
CMOS OUT
CMOS I/O
-
Function
Non-Inverting input. Connections to the front-end differential amplifier.
Inverting input. Connections to the front-end differential amplifier.
Gain select. Gives access to output of front-end differential amplifier for
connection of feedback resistor.
Reference voltage output, nominally VDD/2. May be used to bias the
inputs at midair.
Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull
down resistor.
Power down (input). Active high power down the device and inhibit the
oscillator internal built-in pull down resistor.
Clock Input
3.579545MHz crystal connected between these pins
Clock Output
completes internal oscillator or ceramics generator.
Negative power supply, normally connected to 0V.
3-state data output enable (input). Logic high enables the outputs Q1
Q4.
3-state data outputs. When enabled by TOE, provide the code
corresponding to the last valid tone-pair received.
Delayed steering output. Presents a logic high when the voltage on St/GT
falls below VTSt.
Early steering output. Presents a logic high immediately when the digital
algorithm detects a recognizable tone-pair (signal condition). Any
momentary loss of signal condition will cause Est to return to a logic low.
Steering input/guard time output (bi-directional). A voltage greater than
VTSt detected as St causes the device to register the detected tone-pair
and update the output latch. A voltage less than VTSt free the device to
accept a new tone-pair. The GT output acts to reset the external steering
time-constant; its state is a function of Est and the voltage on St.
Positive power supply.
Application Circuit (for Reference only)
0.1μ
Vin+ R1
Vin- R2
0.1μ R3 R4
180P
5V
R5
3.5795MHz
30p 30p
5V
IN+
IN-
GS
VREF
INH
PWDN
OSC1
OSC2
VSS
0.1μ
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
0.1μ
300k
3/4
Datasheet pdf - http://www.DataSheet4U.net/
Page 3
Part Number CS9370
Manufactur Semico
Description DTMF Receiver
Total Page 4 Pages
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