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Fairchild Semiconductor
Fairchild Semiconductor

CD4046BC Datasheet

Micropower Phase-Locked Loop


CD4046BC Datasheet Preview


October 1987
Revised March 2002
CD4046BC
Micropower Phase-Locked Loop
General Description
The CD4046BC micropower phase-locked loop (PLL) con-
sists of a low power, linear, voltage-controlled oscillator
(VCO), a source follower, a zener diode, and two phase
comparators. The two phase comparators have a common
signal input and a common comparator input. The signal
input can be directly coupled for a large voltage signal, or
capacitively coupled to the self-biasing amplifier at the sig-
nal input for a small voltage signal.
Phase comparator I, an exclusive OR gate, provides a digi-
tal error signal (phase comp. I Out) and maintains 90°
phase shifts at the VCO center frequency. Between signal
input and comparator input (both at 50% duty cycle), it may
lock onto the signal input frequencies that are close to har-
monics of the VCO center frequency.
Phase comparator II is an edge-controlled digital memory
network. It provides a digital error signal (phase comp. II
Out) and lock-in signal (phase pulses) to indicate a locked
condition and maintains a 0° phase shift between signal
input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an
output signal (VCO Out) whose frequency is determined by
the voltage at the VCOIN input, and the capacitor and resis-
tors connected to pin C1A, C1B, R1 and R2.
The source follower output of the VCOIN (demodulator Out)
is used with an external resistor of 10 kor more.
The INHIBIT input, when high, disables the VCO and
source follower to minimize standby power consumption.
The zener diode is provided for power supply regulation, if
necessary.
Features
s Wide supply voltage range: 3.0V to 18V
s Low dynamic power consumption: 70 µW (typ.)
at fo = 10 kHz, VDD = 5V
s VCO frequency: 1.3 MHz (typ.) at VDD = 10V
s Low frequency drift: 0.06%/°C at VDD = 10V with
temperature
s High VCO linearity: 1% (typ.)
Applications
• FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discrimination
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Tone decoding
• FSK modulation
• Motor speed control
Ordering Code:
Order Number Package Number
Package Description
CD4046BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4046BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2002 Fairchild Semiconductor Corporation DS005968
www.fairchildsemi.com
Page 1

Connection Diagram
Block Diagram
Top View
FIGURE 1.
www.fairchildsemi.com
2
Page 2

Absolute Maximum Ratings(Note 1)
(Note 2)
DC Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
0.5 to +18 VDC
0.5 to VDD +0.5 VDC
65°C to +150°C
700 mW
500 mW
260°C
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD)
3 to 15 VDC
Input Voltage (VIN)
0 to VDD VDC
Operating Temperature Range (TA)
55°C to +125°C
Note 1: Absolute Maximum Ratingsare those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of Recom-
mended Operating Conditionsand Electrical Characteristicsprovides
conditions for actual device operation.
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
Symbol
Parameter
Conditions
IDD Quiescent Device Current Pin 5 = VDD, Pin 14 = VDD,
Pin 3, 9 = VSS
VDD = 5V
VDD = 10V
VDD = 15V
Pin 5 = VDD, Pin 14 = Open,
Pin 3, 9 = VSS
VDD = 5V
VDD = 10V
VDD = 15V
VOL LOW Level Output Voltage VDD = 5V
VDD = 10V
VDD = 15V
VOH
HIGH Level Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VIL LOW Level Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
Comparator and Signal In
VDD = 10V, VO = 1V or 9V
VDD = 15V, VO = 1.5V or 13.5V
VIH HIGH Level Input Voltage
VDD = 5V, VO = 0.5V or 4.5V
Comparator and Signal In
VDD = 10V, VO = 1V or 9V
VDD = 15V, VO = 1.5V or 13.5V
IOL
LOW Level Output Current
VDD = 5V, VO = 0.4V
(Note 4)
VDD = 10V, VO = 0.5V
VDD = 15V, VO = 1.5V
IOH
HIGH Level Output Current
VDD = 5V, VO = 4.6V
(Note 4)
VDD = 10V, VO = 9.5V
VDD = 15V, VO = 13.5V
IIN Input Current
All Inputs Except Signal Input
VDD = 15V, VIN = 0V
VDD = 15V, VIN = 15V
CIN Input Capacitance
PT Total Power Dissipation
Any Input (Note 3)
fo = 10 kHz, R1 = 1 M,
R2 = ∞, VCOIN = VCC/2
VDD = 5V
VDD = 10V
VDD = 15V
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: IOH and IOL are tested one output at a time.
55°C
Min Max
+25°C
Min Typ Max
+125°C
Units
Min Max
5 0.005 5
10 0.01 10
20 0.015 20
150
300 µA
600
4.95
9.95
14.95
3.5
7.0
11.0
0.64
1.6
4.2
0.64
1.6
4.2
45
450
1200
0.05
0.05
0.05
1.5
3.0
4.0
4.95
9.95
14.95
3.5
7.0
11.0
0.51
1.3
3.4
0.51
1.3
3.4
5
20
50
0
0
0
5
10
15
2.25
4.5
6.25
2.75
5.5
8.25
0.88
2.25
8.8
0.88
2.25
8.8
35
350
900
0.05
0.05
0.05
1.5
3.0
4.0
4.95
9.95
14.95
3.5
7.0
11.0
0.36
0.9
2.4
0.36
0.9
2.4
185
650
1500
0.05
0.05
0.05
1.5
3.0
4.0
µA
V
V
V
V
mA
mA
0.1
0.1
105 0.1
105 0.1
1.0
1.0
7.5
µA
pF
0.07
0.6
2.4
mW
3 www.fairchildsemi.com
Page 3
Part Number CD4046BC
Manufactur Fairchild Semiconductor
Description Micropower Phase-Locked Loop
Total Page 14 Pages
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