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BD9275F Datasheet

Silicon Monolithic Integrated Circuit


BD9275F Datasheet Preview


1/4
STRUCTURE
NAME OF PRODUCT
Silicon Monolithic Integrated Circuit
DC-AC Inverter Control IC
TYPE
FUNCTION
BD9275F
・Using 20V process / 1ch control with Push-Pull
・Accuracy of drive output frequency:3.5%(IC Only/Built-in CT Capacitor)
・High accuracy timer latch current(±15%)
・Built-in FAIL function
・Adjustable latch timing
・Adjustable slow start time
・Lamp current and voltage sense feedback control
・Mode-selectable the operating or stand-by mode by STB pin (Typ.=0uA )
○Absolute Maximum Ratings(Ta = 25℃)
Parameter
Symbol
Limits
Unit
Supply Voltage
VCC 20
V
OUTPUT PIN Voltage
N1, N2
20
V
Operating Temperature Range
Topr
-40~+85
Storage Temperature Range
Tstg
-55~+150
Maximum Junction Temperature
Tjmax
+150
Power Dissipation
Pd SOP18:562* mW
*1Pd derate at -4.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇動作範囲
項目
Supply voltage
Input Frequency Ratio PWM_IN PIN
DRIVER frequency
記号
VCC
F_PWM_IN
F_OUT
範囲
8.0 ~ 18.0
0.060~0.5
20 ~ 90
単位
V
kHz
kHz
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REV. B
Page 1

○Electric Characteristics(Ta=25℃、VCC=12V、STB=3.0V)
Item
((WHOLE DEVICE))
SYMBOL
MIN.
Operating current
Stand-by current
((STAND BY CONTROL))
Icc1
Icc2
Stand-by voltage H
Stand-by voltage L
STB PIN pull down resistor
((VCC UVLO BLOCK)))
VSTBH
VSTBL
RSTB
2
-0.3
180
Operating voltage
Hesteresis width
((OSC BLOCK))
VCC_UVLO
⊿UVLO_HYS
7.2
0.3
RT pin Voltage
SRT ON resistance
((PWM Dimming Block))
PWM_IN PIN voltage H
PWM_IN PIN voltage L
PWM_IN PIN pull down resistor
((FEED BACK BLOCK))
VRT
RSRT
VPWMIN_H
VPWMIN_L
R_PWMIN
1.300
2.4
-0.3
1000
IS threshold voltage
VIS
VS threshold voltage
VVS
IS source current
IIS
IS COMP detect voltage
VISCOMP
((SLOW START BLOCK))
SS term END Voltage
VSS
Soft start current
ISS
((COMP BLOCK))
COMP over voltage
detect voltage
VCOMPH
Hysterisis width (COMP)
⊿VCOMPH
COMP PIN pull down resistor
RCOMP
FAIL ON resistance
RFAIL
((OUTPUT BLOCK))
N1,N2 PIN output
sink resistance
N1,N2 PIN output
source resistance
RsinkN
RsourceN
MAX DUTY
MAX DUTY
Drive output frequency
FOUT
((TIMER BLOCK))
1.225
1.200
16
0.565
2.400
1.7
1.900
0.100
1000
1.5
4.5
45
48.25
Timer Latch setting voltage
VCP 2.900
Timer Latch setting current
ICP
1.7
(This product is not designed to be radiation-resistant.)
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LIMIT
TYP.
2.0
0
-
-
375
7.5
0.5
1.500
75
-
-
2000
1.250
1.250
20
0.625
2.500
2.0
2.000
0.200
2000
75
3.0
9
47.0
50
3.000
2.0
MAX.
4.0
20
VCC
0.8
750
7.8
0.7
1.700
150
5
0.8
4000
1.275
1.300
24
0.685
2.600
2.3
2.100
0.300
4000
150
6.0
18
49.5
51.75
3.100
2.3
UNIT
CONDITION
mA RT=100kΩ, FB=GND, IS=1.5V
μA VSTB=0V
V System ON
V System OFF
kΩ VSTB=2V
V VCC=6V→8V sweep
V VCC=8V→6V sweep
V RT=100kΩ
Ω VSRT=0.1V
V VPWM_IN=0V⇒3.0V
V VPWM_IN=3.0V⇒0V
kΩ VPWM_I=5V
V
V
μA IS=1.0V
V IS=1.3V→0.5V
V VSS=0V⇒3V
μA VSS=1.0V IS=1.5V
V VSS>2.5V VCOMP=1.5V→2.5V
V VSS<2.0V VCOMP=2.5V→1.5V
kΩ COMP=5V
Ω VFAIL=0.1V
Ω IIN=100mA
Ω IIN=-100mA
% FOUT=50kHz
kHz RT=100kΩ
V VCP=0V⇒3.2V
μA CP=1.0V IS=1.5V COMP=3.0V
2/4
REV. B
Page 2

〇Package Dimensions
MMAAXX1111..5555 ((iinncclluuddee.. BBUURRRR))
Device Name
BD9275F
Lot No.
3/4
SOP-16 (Unit:mm)
〇PIN No.・PIN NAME・FUNCTION
No. PIN
Function
1 VCC Supply voltage input
2 STB Stand-by switch
External resistor from SRT to RT for adjusting
3 SRT the triangle oscillator
External resistor from SRT to RT for adjusting
4 RT the triangle oscillator
5 GND GROUND
6 FB Error amplifier output
7 IS Error amplifier input
8 VS Error amplifier input
BD9275F
No. PIN
16 N1 NMOS FET driver
15 N2 NMOS FET driver
Function
14 PGND Ground for FET drivers
13 PWM_IN Dimming pulse signal input pin
12 SS External capacitor from SS to GND for Soft Start Control
11 CP External capacitor from CP to GND for Timer Latch
10 FAIL Error signal output pin
9 COMP Over voltage detect pin
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REV. B
Page 3

4/4
NOTE FOR USE
1. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings.
Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical
protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum
ratings.
2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended
operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating
ranges, however the variation will be small.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL voltage should be under VCC voltage
+0.3V
6. BD9275F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee
its operation of the thermal shutdown circuit is assumed.
7. When modifying the external circuit components, make sure to leave an adequate margin for external components actual
value and tolerance as well as dispersion of the IC.
8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.
Make sure to leave adequate margin for this IC variation.
9. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate.
10. Under operating Slow Start Control (SS is less than 2.5V), It does not operate Timer Latch.
11. By STB voltage is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state
(0.8~2.0V).
12. The pin connected a connector need to connect to the resistor for electrical surge destruction.
13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is
formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by
which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input
pin.
Resistance
Transistor (NPN)
(PinA)
(PinB)
B
C
E
GND
P
P
N
P
P substrate
GND
Parasitic diode
N
N
P substrate
GND
Parasitic diode
N
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(PinA)
Parasitic diode
GND
(PinB)
B C
E
GND
Parasitic diode
Other adjacent components
Fig-1 Simplified structure of a Bipolar IC
REV. B
Page 4
Part Number BD9275F
Manufactur Rohm
Description Silicon Monolithic Integrated Circuit
Total Page 5 Pages
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BD9275F datasheet
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