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Analog Devices
Analog Devices

AD9995 Datasheet

12-Bit CCD Signal Processor with Precision Timing Generator


AD9995 Datasheet Preview


12-Bit CCD Signal Processor with
Precision Timing Generator
AD9995
FEATURES
6-Phase Vertical Transfer Clock Support
Correlated Double Sampler (CDS)
6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
12-Bit 36 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with <600 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Input
56-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
GENERAL DESCRIPTION
The AD9995 is a highly integrated CCD signal processor for
digital still camera and camcorder applications. It includes a
complete analog front end with A/D conversion, combined with a
full-function programmable timing generator. The timing genera-
tor is capable of supporting both 4- and 6-phase vertical clocking.
A Precision Timing core allows adjustment of high speed clocks
with less than 600 ps resolution at 36 MHz operation.
The AD9995 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, CDS, VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 56-lead LFCSP, the AD9995 is speci-
fied over an operating temperature range of –20°C to +85°C.
CCDIN
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
CDS
6dB TO 42dB
VGA
VREF
AD9995
12-BIT
ADC
12
DOUT
RG
H1–H4
V1–V6
VSG1–VSG5
HORIZONTAL
4 DRIVERS
6
V-H
5 CONTROL
INTERNAL CLOCKS
CLAMP
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
DCLK
MSHUT
STROBE
VSUB SUBCK
HD VD SYNC CLI CLO SL SCK DATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
Page 1

AD9995
TABLE OF CONTENTS
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
AD9995 Analog Specifications . . . . . . . . . . . . . . . . . . . . . . 4
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . 5
PACKAGE THERMAL CHARACTERISTICS. . . . . . . . . . . 5
ORDERING GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . 6
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
EQUIVALENT CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . 7
TYPICAL PERFORMANCE CHARACTERISTICS . . . . . . 8
SYSTEM OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PRECISION TIMING HIGH SPEED TIMING
GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
High Speed Clock Programmability . . . . . . . . . . . . . . . . . 10
H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . 11
Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HORIZONTAL CLAMPING AND BLANKING . . . . . . . . 13
Individual CLPOB and PBLK Patterns. . . . . . . . . . . . . . . 13
Individual HBLK Patterns . . . . . . . . . . . . . . . . . . . . . . . . 13
Generating Special HBLK Patterns. . . . . . . . . . . . . . . . . . 14
Generating HBLK Line Alternation . . . . . . . . . . . . . . . . . 14
HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . . 15
VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . . 16
Vertical Pattern Groups (VPAT) . . . . . . . . . . . . . . . . . . . . 17
Vertical Sequences (VSEQ) . . . . . . . . . . . . . . . . . . . . . . . . 18
Complete Field: Combining V-Sequences . . . . . . . . . . . . . 19
Generating Line Alternation for V-Sequence and HBLK . . 20
Second V-Pattern Group during VSG Active Line . . . . . . . 20
Sweep Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Vertical Sensor Gate (Shift Gate) Patterns . . . . . . . . . . . . . 22
MODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VERTICAL TIMING EXAMPLE . . . . . . . . . . . . . . . . . . . . 24
Important Note about Signal Polarities . . . . . . . . . . . . . . . 24
SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . . 26
Normal Shutter Operation . . . . . . . . . . . . . . . . . . . . . . . . 26
High Precision Shutter Operation . . . . . . . . . . . . . . . . . . . 26
Low Speed Shutter Operation . . . . . . . . . . . . . . . . . . . . . . 26
SUBCK Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Readout after Exposure. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Using the TRIGGER Register . . . . . . . . . . . . . . . . . . . . . . 27
VSUB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MSHUT and STROBE Control . . . . . . . . . . . . . . . . . . . . 28
TRIGGER Register Limitations . . . . . . . . . . . . . . . . . . . . 29
EXPOSURE AND READOUT EXAMPLE . . . . . . . . . . . . 30
AFE DESCRIPTION AND OPERATION . . . . . . . . . . . . . 31
DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 31
Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
POWER-UP AND SYNCHRONIZATION . . . . . . . . . . . . . 33
Recommended Power-Up Sequence for Master Mode. . . . 33
Generating Software SYNC without
External SYNC Signal . . . . . . . . . . . . . . . . . . . . . . . . . 33
SYNC during Master Mode Operation . . . . . . . . . . . . . . . 34
Power-Up and Synchronization in Slave Mode . . . . . . . . . 34
STANDBY MODE OPERATION . . . . . . . . . . . . . . . . . . . . 34
CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . . 36
SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . 37
Register Address Banks 1 and 2. . . . . . . . . . . . . . . . . . . . . 38
Updating of New Register Values. . . . . . . . . . . . . . . . . . . . 39
COMPLETE LISTING OF REGISTER BANK 1 . . . . . . . 40
COMPLETE LISTING OF REGISTER BANK 2 . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 59
–2– REV. 0
Page 2

AD9995–SPECIFICATIONS
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1–H4 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
POWER DISSIPATION (See TPC 1 for Power Curves)
36 MHz, Typ Supply Levels, 100 pF H1–H4 Loading
Power from HVDD Only*
Standby 1 Mode
Standby 2 Mode
Standby 3 Mode
MAXIMUM CLOCK RATE (CLI)
Min Typ
–20
–65
2.7 3.0
2.7 3.0
2.7 3.0
2.7 3.0
2.7 3.0
2.7 3.0
360
130
130
12
0.5
36
*The total power dissipated by the HVDD supply may be approximated using the equation
[ ]Total HVDD Power = CLOAD × HVDD × Pixel Frequency × HVDD × Number of Houtputs used
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ IOH = 2 mA
Low Level Output Voltage @ IOL = 2 mA
RG and H-DRIVER OUTPUTS (H1–H4)
High Level Output Voltage @ Max Current
Low Level Output Voltage @ Max Current
Maximum Output Current (Programmable)
Maximum Load Capacitance (For Each Output)
Specifications subject to change without notice.
Symbol
VIH
VIL
IIH
IIL
CIN
VOH
VOL
VOH
VOL
Min Typ
2.1
10
10
10
2.2
VDD – 0.5
30
100
Max
+85
+150
3.6
3.6
3.6
3.6
3.6
3.6
Unit
°C
°C
V
V
V
V
V
V
mW
mW
mW
mW
mW
MHz
Max Unit
V
0.6 V
µA
µA
pF
V
0.5 V
V
0.5 V
mA
pF
REV. 0
–3–
Page 3

AD9995
ANALOG SPECIFICATIONS (AVDD = 3.0 V, fCLI = 36 MHz, Typical Timing Specifications, TMIN to TMAX, unless otherwise noted.)
Parameter
Min Typ
Max
Unit
Notes
CDS*
Allowable CCD Reset Transient
Max Input Range before Saturation
Max CCD Black Pixel Amplitude
1.0
500
±50
mV
V p-p
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (VGA Code 0)
Max Gain (VGA Code 1023)
1024
Guaranteed
6
42
Steps
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level (Code 0)
Max Clamp Level (Code 255)
256 Steps
Measured at ADC output.
0 LSB
255 LSB
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
12 Bits
–1.0 ±0.5 +1.0 LSB
Guaranteed
2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
2.0 V
1.0 V
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 0)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
*Input signal characteristics defined as follows:
5.0
40.5
5.5
41.5
0.2
0.8
50
Includes entire signal chain.
6.0 dB
Gain = (0.0351 Code) + 6 dB
42.5 dB
% 12 dB gain applied.
LSB rms AC grounded input, 6 dB gain applied.
dB Measured with step change on supply.
500mV TYP
RESET TRANSIENT
50mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
Specifications subject to change without notice.
–4– REV. 0
Page 4
Part Number AD9995
Manufactur Analog Devices
Description 12-Bit CCD Signal Processor with Precision Timing Generator
Total Page 60 Pages
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