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Microchip Technology
Microchip Technology

93LC46 Datasheet

1K/2K/4K 2.0V Microwire Serial EEPROM


93LC46 Datasheet Preview


M
93LC46/56/66
1K/2K/4K 2.0V Microwire® Serial EEPROM
FEATURES
• Single supply with programming operation down
to 2.0V (Commercial only)
• Low power CMOS technology
- 1 mA active current typical
- 5 µA standby current (typical) at 3.0V
• ORG pin selectable memory configuration
- 128 x 8 or 64 x 16-bit organization (93LC46)
- 256 x 8 or 128 x 16-bit organization(93LC56)
- 512 x 8 or 256 x 16-bit organization(93LC66)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed on
93LC56 and 93LC66
• 1,000,000 E/W cycles guaranteed on 93LC46
• Data retention > 200 years
• 8-pin PDIP/SOIC and 14-pin SOIC package
(SOIC in JEDEC and EIAJ standards)
• Temperature ranges supported
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
PACKAGE TYPES
BLOCK DIAGRAM
VCC
VSS
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
COUNTER
DI
CS
CLK
DATA REGISTER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
DESCRIPTION
The Microchip Technology Inc. 93LC46/56/66 are 1K,
2K, and 4K low-voltage serial Electrically Erasable
PROMs. The device memory is configured as x8 or x16
bits, depending on the ORG pin setup. Advanced
CMOS technology makes these devices ideal for
low-power, nonvolatile memory applications. The
93LC46/56/66 is available in standard 8-pin DIP and 8/
14-pin surface mount SOIC packages. The 93LC46X/
56X/66X are only offered in an “SN” package.
SOIC
DIP
CS 1
CLK 2
DI 3
DO 4
8 VCC
CS
7 NU CLK
6 ORG DI
5 VSS
DO
SOIC
18
27
36
45
SOIC
VCC
NU
NU VCC
ORG CS
VSS CLK
1
2
3
4
8
7
6
5
NC
CS
CLK
ORG NC
VSS DI
DO DO
DI NC
1
2
3
4
5
6
7
14 NC
13 Vcc
12 NU
11 NC
10 ORG
9 VSS
8 NC
© 1997 Microchip Technology Inc.
DS11168L-page 1
Page 1

93LC46/56/66
1.0 ELECTRICAL
CHARACTERISTICS
PIN function Table
Name
Function
1.1 Maximum Ratings*
Vcc ...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to Vcc +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
CS
CLK
DI
DO
VSS
ORG
NU
NC
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Not Utilized
No Connect
Power Supply
TABLE 1-1 DC AND AC ELECTRICAL CHARACTERISTICS
Parameter
Commercial (C): Vcc = +2.0V to +6.0V (C): Tamb = 0˚C to +70˚C
Industrial (I): Vcc = +2.5V to +6.0V (I): Tamb = -40˚C to +85˚C
Symbol
Min.
Max.
Units
Conditions
High level input voltage
VIH1
2.0 Vcc +1
VIH2 0.7 Vcc Vcc +1
V VCC 2.7V
V VCC < 2.7V
Low level input voltage
VIL1 -0.3
0.8
V VCC 2.7V
VIL2
-0.3 0.2 Vcc
V VCC < 2.7V
Low level output voltage
VOL1
VOL2
0.4
0.2
V IOL = 2.1 mA; Vcc = 4.5V
V IOL =100 µA; Vcc = Vcc Min.
High level output voltage
VOH1
VOH2
2.4
Vcc-0.2
V IOH = -400 µA; Vcc = 4.5V
V IOH = -100 µA; Vcc = Vcc Min.
Input leakage current
ILI -10 10 µA VIN = 0.1V to Vcc
Output leakage current
ILO -10 10 µA VOUT = 0.1V to Vcc
Pin capacitance
CIN, COUT
7
pF VIN/VOUT = 0 V (Notes 1 & 3)
(all inputs/outputs)
Tamb = +25°C, FCLK = 1 MHz
ICC read
1 mA FCLK = 2 MHz; Vcc = 6.0V
Operating current
500 µA FCLK = 1 MHz; Vcc = 3.0V
ICC write
3 mA FCLK = 2 MHz; Vcc = 6.0V (Note 3)
Standby current
ICCS — 100 µA CLK = CS = 0V; Vcc = 6.0V
30 µA CLK = CS = 0V; Vcc = 3.0V
Clock frequency
FCLK
2 MHz Vcc 4.5V
1 MHz Vcc < 4.5V
Clock high time
TCKH
250
ns
Clock low time
TCKL
250
ns
Chip select setup time
TCSS
50
ns Relative to CLK
Chip select hold time
TCSH
0
— ns Relative to CLK
Chip select low time
TCSL
250
ns
Data input setup time
TDIS
100
ns Relative to CLK
Data input hold time
TDIH
100
ns Relative to CLK
Data output delay time
TPD — 400 ns CL = 100 pF
Data output disable time
TCZ
100
ns CL = 100 pF (Note 3)
Status valid time
TSV — 500 ns CL = 100 pF
TWC
10
ms ERASE/WRITE mode (Note 2)
Program cycle time
TEC — 15 ms ERAL mode
TWL
30
ms WRAL mode
Endurance
93LC46
— 1M — cycles 25°C, Vcc = 5.0V, Block Mode (Note 4)
93LC56/66
— 10M —
Note 1: This parameter is tested at Tamb = 25˚C and FCLK = 1 MHz.
2: Typical program cycle time is 4 ms per word.
3: This parameter is periodically sampled and not 100% tested.
4: This application is not tested but guaranteed by characterization. For endurance estimates in a specific applica-
tion, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS11168L-page 2
© 1997 Microchip Technology Inc.
Page 2

2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device. A low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93LCXX.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1 to Table 2-6). CLK and DI then become don't
care inputs waiting for a new START condition to be
detected.
Note: CS must go low between consecutive
instructions.
93LC46/56/66
2.3 Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (TPD after the posi-
tive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation has
been initiated.
The status signal is not available on DO, if CS is held
low or high during the entire WRITE or ERASE cycle. In
all other cases DO is in the HIGH-Z mode. If status is
checked after the ERASE/WRITE cycle, a pull-up
resistor on DO is required to read the READY signal.
2.5 Organization (ORG)
When ORG is tied to VSS, the (x8) memory organiza-
tion is selected. When ORG is connected to Vcc or
floated, the (x16) memory organization is selected.
ORG can only be floated for clock speeds of 1 MHz or
less for the (X16) memory organization. For clock
speeds greater than 1 MHz, ORG must be tied to Vcc
or VSS.
© 1997 Microchip Technology Inc.
DS11168L-page 3
Page 3

93LC46/56/66
TABLE 2-1
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-2
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-3
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-4
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-5
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-6
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
SB Opcode
1 11
1 00
1 00
1 00
1 10
1 01
1 00
Address
A6 A5 A4 A3 A2 A1 A0
10XXXXX
00XXXXX
11XXXXX
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
01XXXXX
Data In
D7 - D0
D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
10
10
10
10
18
18
18
INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
SB Opcode
1 11
1 00
1 00
1 00
1 10
1 01
1 00
Address
A5 A4 A3 A2 A1 A0
10XXXX
00XXXX
11XXXX
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
01XXXX
Data In
D15 - D0
D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
9
9
9
9
25
25
25
INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
SB Opcode
1 11
1 00
1 00
1 00
1 10
1 01
1 00
Address
X A7 A6 A5 A4 A3 A2 A1 A0
10XXXXXXX
00XXXXXXX
11XXXXXXX
X A7 A6 A5 A4 A3 A2 A1 A0
X A7 A6 A5 A4 A3 A2 A1 A0
01XXXXXXX
Data In
D7 - D0
D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
12
12
12
12
20
20
20
INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
SB Opcode
1 11
1 00
1 00
1 00
1 10
1 01
1 00
Address
X A6 A5 A4 A3 A2 A1 A0
10XXXXXX
00XXXXXX
11XXXXXX
X A6 A5 A4 A3 A2 A1 A0
X A6 A5 A4 A3 A2 A1 A0
01XXXXXX
Data In
D15 - D0
D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
11
11
11
11
27
27
27
INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
SB Opcode
1 11
1 00
1 00
1 00
1 10
1 01
1 00
Address
A8 A7 A6 A5 A4 A3 A2 A1 A0
10XXXXXXX
00XXXXXXX
11XXXXXXX
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
01XXXXXXX
Data In
D7 - D0
D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
12
12
12
12
20
20
20
INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
SB Opcode
1 10
1 00
1 11
1 00
1 01
1 00
1 00
Address
A7 A6 A5 A4 A3 A2 A1 A0
11XXXXXX
A7 A6 A5 A4 A3 A2 A1 A0
10XXXXXX
A7 A6 A5 A4 A3 A2 A1 A0
01XXXXXX
00XXXXXX
Data In
D15 - D0
D15 - D0
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
27
11
11
11
27
27
11
DS11168L-page 4
© 1997 Microchip Technology Inc.
Page 4
Part Number 93LC46
Manufactur Microchip Technology
Description 1K/2K/4K 2.0V Microwire Serial EEPROM
Total Page 12 Pages
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