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Philips
Philips

74HCT164 Datasheet

8-bit serial-in/parallel-out shift register


74HCT164 Datasheet Preview


INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT164
8-bit serial-in/parallel-out shift
register
Product specification
File under Integrated Circuits, IC06
December 1990
Page 1

Philips Semiconductors
8-bit serial-in/parallel-out shift register
Product specification
74HC/HCT164
FEATURES
Gated serial data inputs
Asynchronous master reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT164 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT164 are 8-bit edge-triggered shift registers
with serial data entry and an output from each of the eight
stages.
Data is entered serially through one of two inputs (Dsa or
Dsb); either input can be used as an active HIGH enable for
data entry through the other input.
Both inputs must be connected together or an unused
input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q0, which
is the logical AND of the two data inputs (Dsa,Dsb) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
tPHL/ tPLH
fmax
CI
CPD
propagation delay
CP to Qn
MR to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per
package
CONDITIONS
TYPICAL
HC HCT
CL = 15 pF; VCC = 5 V
12
11
14
16
78 61
3.5 3.5
notes 1 and 2
40
40
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
UNIT
ns
ns
MHz
pF
pF
December 1990
2
Page 2

Philips Semiconductors
8-bit serial-in/parallel-out shift register
Product specification
74HC/HCT164
PIN DESCRIPTION
PIN NO.
1, 2
3, 4, 5, 6, 10, 11, 12, 13
7
8
9
14
SYMBOL
Dsa, Dsb
Q0 to Q7
GND
CP
MR
VCC
NAME AND FUNCTION
data inputs
outputs
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Page 3

Philips Semiconductors
8-bit serial-in/parallel-out shift register
Product specification
74HC/HCT164
Fig.4 Functional diagram.
APPLICATIONS
Serial data transfer
FUNCTION TABLE
OPERATING MODES
reset (clear)
shift
MR
L
H
H
H
H
INPUTS
CP
X
Dsa
X
l
l
h
h
Dsb
X
l
h
l
h
Q0
L
L
L
L
H
OUTPUTS
Q1 Q7
L L
q0 q6
q0 q6
q0 q6
q0 q6
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the
LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
December 1990
Fig.5 Logic diagram.
4
Page 4
Part Number 74HCT164
Manufactur Philips
Description 8-bit serial-in/parallel-out shift register
Total Page 8 Pages
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