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Philips
Philips

74F74 Datasheet

Dual D-type flip-flop


74F74 Datasheet Preview


INTEGRATED CIRCUITS
74F74
Dual D-type flip-flop
Product specification
Supercedes data of 1990 Oct 23
IC15 Data Handbook
Philips
Semiconductors
1996 Mar 12
Page 1

Philips Semiconductors
Dual D-type flip-flop
Product specification
74F74
FEATURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F74 is a dual positive edge-triggered D-type flip-flop featuring
individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input. When
set and reset are inactive (high), data at the D input is transferred to
the Q and Q outputs on the low-to-high transition of the clock. Data
must be stable just one setup time prior to the low-to-high transition of
the clock for predictable operation. Clock triggering occurs at a
voltage level and is not directly related to the transition time of the
positive-going pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels of the output.
PIN CONFIGURATION
RD0 1
D0 2
CP0 3
SD0 4
Q0 5
Q0 6
GND 7
14 VCC
13 RD1
12 D1
11 CP1
10 SD1
9 Q1
8 Q1
SF00045
TYPE
74F74
TYPICAL fmax
125MHz
TYPICAL SUPPLY CURRENT (TOTAL)
11.5mA
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F74N
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°C
I74F74N
N74F74D
I74F74D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
D0, D1
Data inputs
1.0/1.0
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
SD0, SD1
Set inputs (active low)
1.0/3.0
RD0, RD1
Reset inputs (active low)
1.0/3.0
Q0, Q1, Q0, Q1
Data outputs
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
PKG. DWG. #
SOT27-1
SOT108-1
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
1.0mA/20mA
3
4
1
11
10
13
VCC = Pin 14
GND = Pin 7
2 12
D0 D1
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
56 98
SF00046
4&
S
3
C1
2
1D
1
R
10
S
11
C2
12 2D
13 R
5
6
9
8
SF00047
1996 Mar 12
2 853 0335 16554
Page 2

Philips Semiconductors
Dual D-type flip-flop
Product specification
74F74
LOGIC DIAGRAM
SD 4, 10
RD 1, 13
CP 3, 11
D 2, 12
VCC = Pin 14
GND = Pin 7
5, 9
Q
6, 8
Q
SF00048
FUNCTION TABLE
INPUTS
OUTPUTS
SD RD CP D Q Q
OPERATING
MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X H H Undetermined*
H H h H L Load ”1”
H H l L H Load ”0”
H H X NC NC Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high clock
transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high clock
transition
NC= No change from the previous setup
X = Don’t care
= Low-to-high clock transition
= Not low-to-high clock transition
* = This setup is unstable and will change when either set or reset
return to the high level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
VCC
VIN
IIN
VOUT
IOUT
Tamb
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Commercial range
Industrial range
Tstg Storage temperature range
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to VCC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VIH
VIL
IIk
IOH
IOL
Tamb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free air temperature range
Commercial range
Industrial range
LIMITS
MIN
NOM
MAX
4.5 5.0 5.5
2.0
0.8
–18
–1
20
0 +70
–40 +85
UNIT
V
V
V
mA
mA
mA
°C
°C
1996 Mar 12
3
Page 3

Philips Semiconductors
Dual D-type flip-flop
Product specification
74F74
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
MIN TYP2 MAX
VOH High-level output voltage
±10%VCC
VCC = MIN, VIL = MAX, VIH = MIN IOH = MAX ±5%VCC
2.5
2.7
3.4
V
V
VOL Low-level output voltage
±10%VCC
VCC = MIN, VIL = MAX, VIH = MIN IOL = MAX ±5%VCC
0.30 0.50
0.30 0.50
V
V
VIK Input clamp voltage
VCC = MIN, II = IIK
-0.73 -1.2
V
II
Input current at maximum input
voltage
VCC = MAX, VI = 7.0V
100 µA
IIH High-level input current
VCC = MAX, VI = 2.7V
20 µA
IIL
Low-level input
current
Dn, CPn VCC = MAX, VI = 0.5V
SDn, RDn VCC = MAX, VI = 0.5V
-0.6 mA
-1.8 mA
IOS
Short-circuit output current3
VCC = MAX
-60 -150 mA
ICC Supply current (total) 4
VCC = MAX
11.5 16
mA
NOTES:
1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2 All typical values are at VCC = 5V, Tamb = 25°C.
3 Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4 Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
fmax Maximum clock frequency Waveform 1
tPLH Propagation delay
tPHL CPn to Qn or Qn
Waveform 1
tPLH
tPHL
Propagation delay
SDn, RDn to Qn or Qn
Waveform 2
VCC = +5.0V
Tamb = +25°C
CL = 50pF, RL = 500
MIN TYP MAX
100 125
3.8 5.3 6.8
4.4 6.2 8.0
3.2 4.6 6.1
3.5 7.0 9.0
LIMITS
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500
MIN MAX
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF, RL = 500
MIN MAX
100 90
3.8 7.8 3.8 8.5
4.4 9.2 4.4 9.2
3.2 7.1 3.2 7.5
3.5 10.5 2.5 10.5
UNIT
MHz
ns
ns
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
tsu (H)
tsu (L)
th (H)
th (L)
tw (H)
tw (L)
tw (L)
trec
Setup time, high or low
Dn to CPn
Hold time, high or low
Dn to CPn
CPn pulse width,
high or low
SDn, RDn pulse width,
low
Recovery time
SDn, RDn to CPn
TEST
CONDITION
Waveform 1
Waveform 1
Waveform 1
VCC = +5.0V
Tamb = +25°C
CL = 50pF, RL = 500
MIN TYP MAX
2.0
3.0
1.0
1.0
4.0
5.0
LIMITS
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500
MIN MAX
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF, RL = 500
MIN MAX
2.0 2.0
3.0 3.0
1.0 1.0
1.0 1.0
4.0 4.0
5.0 5.0
UNIT
ns
ns
ns
Waveform 2 4.0
4.0 4.0 ns
Waveform 3 2.0
2.0 2.0 ns
1996 Mar 12
4
Page 4
Part Number 74F74
Manufactur Philips
Description Dual D-type flip-flop
Total Page 8 Pages
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