RAD HARD 4.5A,
500KHz STEP DOWN
4707 Dey Road Liverpool, N.Y. 13088
Rad Hard RH1959MILDICE
Radiation Tested to TBD Krad(Si) (Method 1019.7 Condition A)
500KHz Constant Switching Frequency:Synchronizable to 1MHz
4.5A Integrated Switch
Internal Slope Compensation
Input Voltage Range from 4.3V to 16V
Cycle by Cycle Current Limit
Output Voltages Down to 1.21V
Contact MSK for MIL-PRF-38534 Qualification Status
The MSK 5059RH is a radiation hardened 500KHz switching regulator controller capable of delivering up to 4.5A of
current to the load. A fixed 500KHz switching frequency allows the use of smaller inductors reducing required board space
for a given design. The 4.5A integrated switch leaves only a few application specific components to be selected by the
designer. The MSK 5059RH simplifies design of high efficiency radiation hardened switching regulators that use a minimum
amount of board space. The device is packaged in a hermetically sealed 16 pin flatpack and is available with straight or gull
Satellite System Power Supply
Step Down Switching Regulator
Microprocessor, FPGA Power Source
High Efficiency Low Voltage Subsystem Power Supply
PRELIMINARY Rev. A 11/09
ABSOLUTE MAXIMUM RATINGS 7
Input Voltage (VIN)
Output Current 8
BOOST Voltage 30V○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
BOOST Above Input Voltage
SHDN Pin Voltage 7V○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
FB Pin Voltage 3.5V○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
FB Pin Current 1mA○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
P Power Dissipation TBDD
Junction Temperature ○
Storage Temperature Range
-65°C to +150°C
TLD Lead Temperature Range
(10 Seconds) 300°C○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
TC Case Operating Temperature
-40°C to +85°C
MSK 5059(K/H/E)RH ○
-55°C to +125°C
1 Unless otherwise specified VIN=5V, VC=1.5V, BOOST=VIN+5V.
2 Guaranteed by design but not tested. Typical parameters are representative of actual device performance but are for reference only.
3 Industrial grade and "E" suffix devices shall be tested to subgroup 1 unless otherwise specified.
4 Military grade devices ("H" and "K" suffix) shall be 100% tested to subgroups 1,2,3 and 4.
5 Subgroup 5 & 6 testing available on request.
6 Subgroup 1,4 TC=+25°C
Subgroup 2,5 TC=+125°C
Subgroup 3,6 TC=-55°C
7 Continuous operation at or above absolute maximum ratings may adversely effect the device performance and/or life cycle.
8 The absolute maximum current of 4.5A applies for duty cycles of 0.75 or lower.
De-rate linearly from 4.5A at D=0.75 to 3.375A at D=100.
9 Pre and Post irradiation limits at 25°C, up to TBD Krad(Si) TID, are identical unless otherwise specified.
2 PRELIMINARY Rev. A 11/09
VIN - The VIN pins connect to the collector of the internal power
switch and provide power to the internal control circuitry and
internal regulator. Very high di/dt is seen at these pins during
switch on and off transitions. High frequency decoupling ca-
pacitors are recommended to minimize voltage spikes. All five
VIN pins should be connected to a low impedence source for
SW - The SW pins are connected to the emitter of the internal
power transistor. These pins rise up to the input voltage during
the on time of the switch and are driven negative when the
power switch turns off. The negative voltage is clamped by the
catch diode and must not go more negative than -0.8V. All five
SW pins must be connected for maximum performance.
BOOST - The BOOST pin provides drive voltage greater that
VIN to the base of the power transistor. Using a voltage greater
than VIN ensures hard saturation of the power switch signifi-
cantly improving overall efficiency. Connect a capacitor between
BOOST and SW to store charge. Connect a diode between VIN
and BOOST to charge the capacitor during the off time of the
FB - The FB (feedback) pin's primary function is to set the out-
put voltage. Use a resistive divider from VOUT to GND to set the
voltage at the feedback pin to 1.21V when the output voltage is
at the desired level. The FB pin provdes two additional func-
tions. If the voltage at the FB pin drops below 0.8V the switch
current limit is reduced. When the voltage at the FB pin drops
below 0.7V the switching frequency is reduced and sync is
disabled. The switching frequency reduces to approximately
100KHz at VFB<=0.4V.
GND - The GND pin provides a return path for all internal control
current and acts as a reference to the error amplifier. It is impor-
tant that it is at the same voltage potential as the load return to
ensure proper regulation. Keep current on the ground between
the load and the MSK 5059RH to a minimum and use heavy
copper traces to minimize voltage drops and regulation error.
VC - The VC pin is the output of the error amplifier and the input
of the peak current comparator. This pin is typically used for
frequency compensation but can also be used as a current clamp
or as an override to the internal error amplifier control. The pin
voltage is typically around 1V at light load and 2V at heavy
load. Driving the pin low will shut down the regulator. Driving it
high will increase the output current. The current into the VC pin
must be limited to 4mA when driving it high.
SETTING THE OUTPUT VOLTAGE
The output voltage of the MSK 5059RH is set with a simple
resistor divider network: see Figure 1 (Typical Application Cir-
cuit). Select the resistor values to divide the desired output down
to equal VFB (1.21V nominal) at the FB pin. Use a 2.5K or lower
value resistor for R2 to keep output error due to FB pin bias
current less than 0.1%.
SELECTING THE INDUCTOR
The inductor is used to filter the square pulses at the SW pin to
an acceptable linear ripple. The inductance value will limit the
maximum available current at different input and output voltages.
See "Maximum Load Current" in the typical performance curves
section of this data sheet. Use the curves to make the initial value
selection. Determine the peak inductor current as follows:
f=the switching frequency in Hz
L=inductor value in Henries
Select an inductor what will not saturate at worst case peak cur-
rent. Calculate the peak to peak inductor current ripple as fol-
Nearly all of the current ripple will be seen by the output capaci-
tance. See selecting the output capacitor.
SELECTING THE OUTPUT CAPACITOR
The output capacitor filters the ripple current from the inductor to
an acceptable ripple voltage seen by the load. The primary factor
in determining voltage ripple is the ESR of the output capacitor.
The voltage ripple can be approximated as follows:
The typical ESR range for an MSK 5059RH application is be-
tween 0.05 and 0.20 ohm. Capacitors within these ESR ranges
typically have enough capacitance value to make the capacitive
tern of the ripple equation insignificant. The capacitive term of
the output voltage ripple lags the ESR term by 90° and can be
calculated as follows:
SHDN - The SHDN (shutdown) pin has two shutdown func-
tions. The first function disables switching when the voltage on
the pin drops below 2.38V (nominal). The second forces a com- Where:
plete shutdown minimizing power consumption when the volt-
C=output capacitance in Farads
age drops below 0.4V (nominal). Pull this pin high or leave
open for normal operation. The 2.38V threshold can be used for
UVLO functions by configuring a resistive divider to VIN and
GND that holds the pin voltage below 2.38V until VIN rises to
the minimum desired voltage.
Select a capacitor or combination of capacitors that can tolerate
the worst-case ripple current with sufficient de-rating. When us-
ing multiple capacitors in parallel to achieve ESR and/or total
capacitance sharing of ripple current between capacitors will be
approximately equal if all of the capacitors are the same type and
SYNC - The SYNC pin is used to synchronize the oscillator to an preferably from the same lot. Low ESR tantalum capacitors are
external clock. It is logic compatible and can be driven to any recommended over aluminum electrolytic. The zero created by
frequency between the free run frequency (500KHz nominal) the ESR of the capacitor is necessary for loop stabilty. A small
and 1MHz. The duty cycle of the input signal must be between amount of ceramic capacitance close to the load to decouple high
10% and 90% to ensure proper synchronization. Tie the SYNC frequency is acceptable but it should not cancel the ESR zero.
pin to GND if it is not used.
3 PRELIMINARY Rev. A 11/09
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