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10H116 Datasheet

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MC10H116
Triple Line Receiver
The MC10H116 is a functional/pinout duplication of the MC10116,
with 100% improvement in propagation delay and no increase in
power–supply current.
Propagation Delay, 1.0 ns Typical
Power Dissipation 85 mW Typ/Pkg (same as MECL 10K)
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
42
53
96
10 7
12 14
13 15
11
VBB*
VCC1 = Pin 1
VCC2 = Pin 16
VEE = Pin 8
When input pin with
bubble goes positive
it’s respective output
pin with bubble goes
positive.
*VBB to be used to supply bias to the MC10H115 only and
bypassed (when used) with 0.01 µF to 0.1 µF capacitor to
ground (0 V). VBB can source < 1.0 mA.
The MC10H115 is designed to be used in sensing differential
signals over long lines. The bias supply (VBB) is made available
to make the device useful as a Schmitt trigger, or in other
applications where a stable reference voltage is necessary.
Active current sources provide these receivers with excellent
common–mode noise rejection. If any amplifier in a package is
not used, one input of that amplifier must be connected to VBB to
prevent unbalancing the current–source bias network.
The MC10H115 does not have internal–input pull– down
resistors. This provides high impedance to the amplifier input
and facilitates differential connections.
Applications:
Low Level Receiver Voltage Level
Schmitt Trigger
Interface
Figure 1. Logic Diagram
VCC1 1 16 VCC2
AOUT 2 15 COUT
AOUT 3 14 COUT
AIN 4 13 CIN
AIN 5 12 CIN
BOUT 6 11 VBB
BOUT 7 10 BIN
VEE 8
9 BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
Figure 2. Dip Pin Assignment
16
1
16
1
1
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CDIP–16
L SUFFIX
CASE 620A
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC10H116L
AWLYYWW
1
16
MC10H116P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10H116
AWLYYWW
16
1
SO–16
D SUFFIX
CASE 751B
16
10H116
AWLYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H116L
CDIP–16
25 Units/Rail
MC10H116P
PDIP–16
25 Units/Rail
MC10H116FN PLCC–20
48 Units/Rail
MC10H116D
SO–16
55 Units/Rail
© Semiconductor Components Industries, LLC, 2001
September, 2001 – Rev. 8
1
Publication Order Number:
MC10H116/D
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Page 1

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MC10H116
MAXIMUM RATINGS
Symbol
Characteristic
VEE Power Supply (VCC = 0)
VI Input Voltage (VCC = 0)
Iout Output Current – Continuous
– Surge
TA Operating Temperature Range
Tstg Storage Temperature Range – Plastic
– Ceramic
Rating
–8.0 to 0
0 to VEE
50
100
0 to +75
–55 to +150
–55 to +165
Unit
Vdc
Vdc
mA
°C
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (Note 2)
0°
Symbol
Characteristic
Min Max
IE
IinH
ICBO
VBB
VOH
VOL
VIH
VIL
VCMR
Power Supply Current
Input Current High
Input Leakage Current
Reference Voltage
High Output Voltage
Low Output Voltage
High Input Voltage (Note 1)
Low Input Voltage (Note 1)
Common Mode
Range (Note 4)
–1.38
–1.02
–1.95
–1.17
–1.95
23
150
1.5
–1.27
–0.84
–1.63
–0.84
–1.48
VPP Input Sensitivity (Note 3)
––
25°
Min Max
– 21
– 95
– 1.0
–1.35 –1.25
–0.98 –0.81
–1.95 –1.63
–1.13 –0.81
–1.95 –1.48
–2.85 to –0.8
150 typ
75°
Min Max
– 23
– 95
– 1.0
–1.31
–1.19
–0.92
–0.735
–1.95
–1.60
–1.07
–0.735
–1.95
–1.45
––
––
Unit
mA
µA
µA
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
mVPP
AC PARAMETERS
tpd Propagation Delay
0.4 1.3 0.4 1.3 0.45 1.45
ns
tr Rise Time
0.5 1.5 0.5 1.6 0.5
1.7
ns
tf Fall Time
0.5 1.5 0.5 1.6 0.5
1.7
ns
1. When VBB is used as the reference voltage.
2. Each MECL 10H series circuit has been designed to meet the specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is
maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
3. Differential input not to exceed 1.0 Vdc.
4. 150 mVp–p differential input required to obtain full logic swing on output.
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MC10H116
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE D
–L–
20
–N– Y BRK
–M–
W
1
V
D
D
B 0.007 (0.180) M T L-M S N S
U 0.007 (0.180) M T L-M S N S
Z
X
VIEW D–D
G1 0.010 (0.250) S T L-M S N S
A 0.007 (0.180) M T L-M S N S
Z
R 0.007 (0.180) M T L-M S N S
H 0.007 (0.180) M T L-M S N S
C
E
G
G1
0.010 (0.250) S T L-M S
0.004 (0.100)
J –T– SEATING
PLANE
VIEW S
NS
K1
K
F
VIEW S
0.007 (0.180) M T L-M S N S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
INCHES
DIM MIN MAX
A 0.385 0.395
B 0.385 0.395
C 0.165 0.180
E 0.090 0.110
F 0.013 0.019
G 0.050 BSC
H 0.026 0.032
J 0.020 ---
K 0.025 ---
R 0.350 0.356
U 0.350 0.356
V 0.042 0.048
W 0.042 0.048
X 0.042 0.056
Y --- 0.020
Z 2_ 10_
G1 0.310 0.330
K1 0.040 ---
MILLIMETERS
MIN MAX
9.78 10.03
9.78 10.03
4.20 4.57
2.29 2.79
0.33 0.48
1.27 BSC
0.66 0.81
0.51 ---
0.64 ---
8.89 9.04
8.89 9.04
1.07 1.21
1.07 1.21
1.07 1.42
--- 0.50
2 _ 10 _
7.88 8.38
1.02 ---
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Part Number 10H116
Manufactur ON Semiconductor
Description Search -----> MC10H116
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