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X22C12DM Datasheet Preview

X22C12DM Datasheet

Nonvolatile Static RAM

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X22C12DM pdf
X22C12
1K Bit
X22C12
Nonvolatile Static RAM
256 x 4
FEATURES
High Performance CMOS
—150ns RAM Access Time
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
Low Power Consumption
—Active: 40mA Max.
—Standby: 100µA Max.
Infinite Array Recall, RAM Read and Write Cycles
Nonvolatile Store Inhibit: VCC = 3.5V Typical
Fully TTL and CMOS Compatible
JEDEC Standard 18-Pin 300-mil DIP
100% Compatible with X2212
—With Timing Enhancements
DESCRIPTION
The X22C12 is a 256 x 4 CMOS NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non-
volatile E2PROM. The NOVRAM design allows data to
be easily transferred from RAM to E2PROM (STORE)
and from E2PROM to RAM (RECALL). The STORE
operation is completed within 5ms or less and the
RECALL is completed within 1µs.
Xicor NOVRAMs are designed for unlimited write opera-
tions to the RAM, either RECALLs from E2PROM or
writes from the host. The X22C12 will reliably endure
1,000,000 STORE cycles. Inherent data retention is
greater than 100 years.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
A0
A1
A2
A3
A4
STORE
RECALL
I/O1
I/O2
I/O3
I/O4
CS
WE
NONVOLATILE E2PROM
MEMORY ARRAY
ROW
SELECT
STATIC RAM
MEMORY ARRAY
CONTROL
LOGIC
INPUT
DATA
CONTROL
COLUMN
I/O CIRCUITS
COLUMN SELECT
A7 A6 A5
STORE
ARRAY
RECALL
VCC
VSS
3817 FHD F01
A7
A4
A3
A2
A1
A0
CS
VSS
STORE
PLASTIC DIP
CERDIP
1 18
2 17
3 16
4 15
5 X22C12 14
6 13
7 12
8 11
9 10
VCC
A6
A5
I/O4
I/O3
I/O2
I/01
WE
RECALL
3817 FHD F02
A7
A4
A3
A2
A1
A0
CS
VSS
STORE
RECALL
SOIC
1 20
2 19
3 18
4 17
X22C12
5 16
6 15
7 14
8 13
9 12
10 11
VCC
A6
A5
I/O4
NC
NC
I/O3
I/O2
I/O1
WE
3815 FHD F10.1
© Xicor, Inc. 1991, 1995 Patents Pending
3817-2.4 7/30/96 T0/C0/D1 SH
1 Characteristics subject to change without notice



Xicor
Xicor

X22C12DM Datasheet Preview

X22C12DM Datasheet

Nonvolatile Static RAM

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X22C12DM pdf
X22C12
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (A0–A7)
The address inputs select a 4-bit memory location
during a read or write operation.
Chip Select (CS)
The Chip Select input must be LOW to enable read or
write operations with the RAM array. CS HIGH will place
the I/O pins in the high impedance state.
Write Enable (WE)
The Write Enable input controls the I/O buffers, deter-
mining whether a RAM read or write operation is en-
abled. When CS is LOW and WE is HIGH, the I/O pins
will output data from the selected RAM address loca-
tions. When both CS and WE are LOW, data presented
at the I/O pins will be written to the selected address
location.
Data In/Data Out (I/O1–I/O4)
Data is written to or read from the X22C12 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CS is HIGH or during either a store or
recall operation.
STORE
The STORE input, when LOW, will initiate the transfer of
the entire contents of the RAM array to the E2PROM
array. The WE and RECALL inputs are inhibited during
the store cycle. The store operation is completed in 5ms
or less.
A store operation has priority over RAM read/write
operations. If STORE is asserted during a read opera-
tion, the read will be discontinued. If STORE is asserted
during a RAM write operation, the write will be immedi-
ately terminated and the store performed. The data at
the RAM address that was being written will be unknown
in both the RAM and E2PROM arrays.
RECALL
The RECALL input, when LOW, will initiate the transfer
of the entire contents of the E2PROM array to the RAM
array. The transfer of data will be completed in 1µs or
less.
An array recall has priority over RAM read/write opera-
tions and will terminate both operations when RECALL
is asserted. RECALL LOW will also inhibit the STORE
input.
Automatic Recall
Upon power-up the X22C12 will automatically recall
data from the E2PROM array into the RAM array.
Write Protection
The X22C12 has three write protect features that are
employed to protect the contents of the nonvolatile
memory.
• VCC Sense—All functions are inhibited when VCC is
<3.5V typical.
• Write Inhibit—Holding either STORE HIGH or
RECALL LOW during power-up or power-down will
prevent an inadvertent store operation and E2PROM
data integrity will be maintained.
• Noise Protection—A STORE pulse of typically less
than 20ns will not initiate a store cycle.
PIN NAMES
Symbol
A0–A7
I/O1–I/O4
WE
CS
RECALL
STORE
VCC
VSS
NC
Description
Address Inputs
Data Inputs/Outputs
Write Enable
Chip Select
Recall
Store
+5V
Ground
No Connect
3817 PGM T01
2


Part Number X22C12DM
Description Nonvolatile Static RAM
Maker Xicor
Total Page 12 Pages
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