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X20C04EMB-15 Datasheet Preview

X20C04EMB-15 Datasheet

Nonvolatile Static RAM

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X20C04EMB-15 pdf
X20C04
4K
X20C04
Nonvolatile Static RAM
512 x 8 Bit
FEATURES
High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
Power-on Recall
—E2PROM Data Automatically Recalled Into
SRAM Upon Power-up
Lock Out Inadvertent Store Operations
Low Power CMOS
—Standby: 250µA
Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
Compatible with X2004
DESCRIPTION
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electri-
cally erasable PROM (E2PROM). The X20C04 is fabri-
cated with advanced CMOS floating gate technology to
achieve low power and wide power-supply margin. The
X20C04 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs,
ROMs, EPROMs, and E2PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 5µs or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.
PIN CONFIGURATION
PLASTIC
CERDIP
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 X20C04 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
NC
NC
OE
NC
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3825 FHD F02
LCC
PLCC
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 NC
A4 7
27 NC
A3 8
A2 9
X20C04
(TOP VIEW)
26 NC
25 OE
A1 10
24 NC
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
3825 FHD F03
©Xicor, Inc. 1992, 1995, 1996 Patents Pending
3825-2.8 7/31/97 T4/C0/D0 SH
1 Characteristics subject to change without notice




Xicor
Xicor

X20C04EMB-15 Datasheet Preview

X20C04EMB-15 Datasheet

Nonvolatile Static RAM

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X20C04EMB-15 pdf
X20C04
PIN DESCRIPTIONS
Addresses (A0–A8)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE, or NE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
both the static RAM and stores to the E2PROM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls all accesses to
the E2PROM array (store and recall functions).
PIN NAMES
Symbol
A0–A8
I/O0–I/O7
WE
CE
OE
NE
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
Nonvolatile Enable
+5V
Ground
No Connect
3825 PGM T01
FUNCTIONAL DIAGRAM
VCC SENSE
EEPROM ARRAY
A3–A6
CE
OE
WE
NE
A0–A2
A7–A8
ROW
SELECT
CONTROL
LOGIC
512 x 8
SRAM
ARRAY
COLUMN
SELECT
&
I/OS
I/O0–I/O7
3825 FHD F01
2




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Xicor

X20C04EMB-15 Datasheet Preview

X20C04EMB-15 Datasheet

Nonvolatile Static RAM

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X20C04EMB-15 pdf
X20C04
DEVICE OPERATION
The CE, OE, WE and NE inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C04.
Nonvolatile Operations
With NE LOW, recall operation is performed in the same
manner as RAM read operation. A recall operation
causes the entire contents of the E2PROM to be written
into the RAM array. The time required for the operation
to complete is 5µs or less. A store operation causes the
entire contents of the RAM array to be stored in the
nonvolatile E2PROM. The time for the operation to
complete is 5ms or less.
Power-Up Recall
Upon power-up (VCC), the X20C04 performs an auto-
matic array recall. When VCC minimum is reached, the
recall is initiated, regardless of the state of CE, OE, WE
and NE.
Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvolatile
memory and the RAM.
• VCC Sense—All functions are inhibited when VCC is
3.5V.
• A RAM write is required before a Store Cycle is
initiated.
• Write Inhibit—Holding either OE LOW, WE HIGH,
CE HIGH, or NE HIGH during power-up and power-
down will prevent an inadvertent store operation.
• Noise Protection—A combined WE, NE, OE and
CE pulse of less than 20ns will not initiate a Store
Cycle.
• Noise Protection—A combined WE, NE, OE and
CE pulse of less than 20ns will not initiate a recall
cycle.
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
3




Part Number X20C04EMB-15
Description Nonvolatile Static RAM
Maker Xicor
Total Page 15 Pages
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