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Toshiba Electronic Components Datasheet

TC58FVM7B2AFT65 Datasheet

128-MBIT (16M x 8 BITS / 8M x 16 BITS) CMOS FLASH MEMORY

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TC58FVM7B2AFT65 pdf
TC58FVM7(T/B)2AFT(65/80)
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128-MBIT (16M × 8 BITS / 8M × 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVM7T2A/B2A is a 134217728-bit, 3.0-V read-only electrically erasable and programmable flash
memory organized as 16777216 words × 8 bits or as 8388608 words × 16 bits. The TC58FVM7T2A/B2A features
commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands
are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The
TC58FVM7T2A/B2A also features a Simultaneous Read/Write operation so that data can be read during a Write or
Erase operation.
FEATURES
Power supply voltage
Access Time (Random/Page)
VDD = 2.3 V~3.6 V
Operating temperature
TC58FVM7T2A/B2AFT65 TC58FVM7T2A/B2AFT80
Ta = −40°C~85°C
VDD
CL = 30 pF CL = 100 pF CL = 30 pF CL = 100 pF
Organization
16M × 8 bits/8M × 16 bits
Functions
Simultaneous Read/Write
Page Read
Auto Program, Auto Page Program
Auto Block Erase, Auto Chip Erase
Fast Program Mode / Acceleration Mode
Program Suspend/Resume
Erase Suspend/Resume
data polling/Toggle bit
2.7~3.6V 65 ns/25 ns 70 ns/30 ns 80 ns/30 ns 85 ns/35 ns
2.3~3.6V 70 ns/30 ns 75 ns/35 ns 85 ns/35 ns 90 ns/40 ns
Power consumption
10 µA (Standby)
15 mA (Program/Erase operation)
55 mA (Random Read operation)
11 mA (Address Increment Read operation)
5 mA (Page Read operation)
Package
TSOP 56-P-1420-0.50A (weight: 0.61g)
block protection, boot block protection
Automatic Sleep, support for hidden ROM area
common flash memory interface (CFI)
Byte/Word Modes
Block erase architecture
8 × 8 Kbytes/255 × 64 Kbytes
Boot block architecture
TC58FVM7T2A: top boot block
TC58FVM7B2A: bottom boot block
Mode control
Compatible with JEDEC standard commands
Erase/Program cycles
105 cycles typ.
2002-10-24 1/68


Toshiba Electronic Components Datasheet

TC58FVM7B2AFT65 Datasheet

128-MBIT (16M x 8 BITS / 8M x 16 BITS) CMOS FLASH MEMORY

No Preview Available !

TC58FVM7B2AFT65 pdf
Ordering information
TC58FVM7(T/B)2AFT(65/80)
TC58 F V M7 T2 A FT 65
Speed version
65 = 65 ns, 80 = 80 ns
Package
FT = TSOP
Design rule
A = 0.16 µm
Function/Boot block architecture/Bank ratio
T2 = Page mode/Top boot block/1:3:3:1
B2 = Page mode/Bottom boot block/1:3:3:1
Capacity
M7 = 128Mbits
Supply Voltage
V = 3V system
Device type
F = NOR Flash memory
Toshiba CMOS E2PROM
Ordering type
TC58FVM7T2AFT65
TC58FVM7B2AFT65
TC58FVM7T2AFT80
TC58FVM7B2AFT80
Boot block
Top
Bottom
Top
Bottom
Speed version
65ns
85ns
Package
TSOP -P-1420-0.50
2002-10-24 2/68


Part Number TC58FVM7B2AFT65
Description 128-MBIT (16M x 8 BITS / 8M x 16 BITS) CMOS FLASH MEMORY
Maker Toshiba
Total Page 30 Pages
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