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Toshiba Electronic Components Datasheet

TC190 Datasheet

System ASIC

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TC190 pdf
TOSHIBA
System ASIC
TC190 Series CMOS ASICs
0.6µ 3.0/3.3V ASIC Family
The 0.6µm, 5V TC190 ASIC series provides higher system per-
formance and device integration with lower power than previous
generation 5V families. Highly accurate delay models, area effi-
cient memory cells and a very fine pitch TAB bonding capability
for high I/O requirements are some of the features of the family
which consists of Gate Array (TC190G), Embedded Array
(TC190E) and Standard Cell (TC190C) ASIC products. The
www.DataShTeCet14U90.cEomis a gate array based product that incorporates the ability
to embed large diffused cell based hardmacrocells and com-
pilable cells (RAM, ROM, DAC, multipliers, PLLs, etc) rather
than building metalized functions. This enables denser, faster,
higher performance ASICS to be designed while still exhibiting
quick “gate array” type turn around times.
Benefits
– Advanced 0.6µ micron CMOS process with fast 240 gate
delays.
– Reduction of gate power by as much as 20 percent over 0.8µm
ASICs.
– 707,000 usable gates provide high levels of integration for
improved performance and board area savings.
– Extensive libraries with a wide range of macrocells,
compilable cells and megacells availible.
– Library compatible with existing TC160G/170G gate arrays for
ease of design migration to 0.6µm technology
– Design Kit support for a wide range of EDA environments.
– VERILOG-XL sign off capability.
– 62µ TAB pad pitch allows higher number of I/O per gate than
previous product generations.
– A wide range of packages are availible, including heat spreader
plastic QFP, TABFP, BGA, tape BGA and others.
– New accurate delay modeling
– Verilog sign-off
System Performance
The high density, high performance TC190 series ASIC family is
manufactured using Toshiba’s 0.6µm double and triple layer
complimentary metal-oxide silicon process. This family provides
sub-micron ASIC density for pure 5V applications, and applica-
tions that are developed to transition over time to 3V. Typical
applications are PC chipsets, graphics, telecommunications, net-
works, set top boxes and systems designed to migrate from 5V to
3V.
The 707K usable gates allow previously unobtainable levels
of integration to be achieved on a 5V ASIC. The TC190 series
supports many complex functions such as multipliers, DACs,
ADCs,RAM, ROM and FIFOs.
The TC190 series offers Toshiba’s high quality and high
capacity manufacturing expertise. A partnership with Toshiba
brings you not only the high quality and reliability ASICs, but
fast prototype turnaround (3 day for gate array), steep production
ramp-up and proven high volume manufacturing capacity.
Packaging
The TC190 series wide range of packaging options provide a
packaging solution for any requirement. New packages are con-
tinuously being developed. Contact your Toshiba sales represen-
tative for the Toshiba Packaging Book for specific package/pin
count information.
Features
TC190G
TC190E/C
– 22K – 707K usable gates
up to 730K
– 14 standard master sizes
21 standard master sizes
– up to 512 wire bonds
Same
– up to 776 TAB bond pads
– 62µ Inner lead bond pads
Same
– Typical core power – 2.63µW/gate/Mhz
– 180+ primitive cells
(scan, standard, high drive cells)
Same
– 450+ I/O cells including (hign drive
{24mA} slew rate control high
speed output buffers)
Compiled cells – sync/async
single, dual, triple port RAM, ROM
Same
Same
– Hard macrocells including those for PCI
bus interface are availible. Some fast
multipliers, adders, ALUs, UARTS timers
and special I/O cells are in development.
– Ability to embed large Compilable, fully
diffused memory blocks provide higher
performance and increased desnsity.
Same
TC190G Two Input NAND Gate Delay Performance
ND2 Gate Delay1
Typical2
Worst Case3
Fanout = 2
240ps
406ps
Fanout = 4
336ps
568ps
Fanout = 6
432ps
731ps
Power Dissipation
at 5V
Power = 2.63µW/gate/MHz
NOTE 1: These typical numbers are for estimation purposes only. Power dissap-
ation is dependent on wire loading and gate switching rates.
Product Brief
TOSHIBA Corporation
1


Toshiba Electronic Components Datasheet

TC190 Datasheet

System ASIC

No Preview Available !

TC190 pdf
TC190G Gate Array Product Summary
Reference
Usable Gates
DLM TLM
I/O Pads
Wirebond TAB
Pads 62µm
TC190G02/ 52
TC190G04/ 54
TC190G06/ 56
TC190G08/ 58
TC190G10/ 60
TC190G12/ 62
TC190G14/ 64
www.DataTSCh1e9e0tG41U6./c6o6m
TC190G20/ 70
TC190G24/ 74
TC190G32/ 82
TC190G36/ 86
TC190G40/ 90
TC190G42/ 92
12,000
22,000
31,000
39,000
47,000
56,000
67,000
82,000
98,000
125,000
175,000
228,000
288,000
404,000
22,000
38,000
54,000
68,000
81,000
99,000
117,000
143,000
171,000
219,000
307,000
400,000
505,000
707,000
80
104
128
144
160
176
192
208
240
272
336
384
432
512
160
208
256
296
324
356
388
428
* Double Layer Metal / Triple Layer Metal
TAB
83µm
120
156
192
220
240
264
288
320
368
416
512
584
656
776
Clock Distribution Network
Toshiba implements clock distribution networks in ASIC designs
using a variety of different topologies including loop, grid, tree or
trunk. The actual topology used depends on the desired clock
skew specification and other design criteria such as power con-
sumption limits and availible gates. Typical on-chip skew delays
TC190E/C Embedded Array and Standard Cell Product
Reference
Usable Gates
DLM TLM
I/O Pads
Wirebond TAB
Pads 62µm
TAB
83µm
TC190E/C02
TC190E/C04
TC190E/C06
TC190E/C08/58
TC190E/C10/60
TC190E/C12/62
TC190E/C14/64
TC190E/C16/66
TC190E/C18/68
TC190E/C20/70
TC190E/C22/72
TC190E/C24/74
TC190E/C26/76
TC190E/C28/78
TC190E/C30/80
TC190E/C32/82
TC190E/C34/84
TC190E/C36/86
TC190E/C38/88
TC190E/C40/90
TC190E/C42/92
12,000
21,000
32,500
40,900
49,300
59,950
71,600
81,050
94,000
107,850
122,700
138,500
155,250
172,950
181,250
199,800
229,350
260,900
294,500
330,150
437,150
66,450
80,200
97,450
116,350
131,450
152,400
174,900
198,950
224,600
251,750
280,450
295,200
325,400
373,500
424,950
479,650
537,700
728,550
80
104
128
144
160
176
192
208
224
240
256
272
288
304
320
336
360
384
408
432
512
152 112
200 148
248 186
288 212
316 236
348 260
380 284
420 312
336
360
384
408
432
456
480
504
540
576
612
648
768
* Double Layer Metal / Triple Layer Metal
will be less than 0.5ns. Toshiba plans to offer tighter links between
logical and physical; design processes, i.e. synthesis, floor plan-
ning and layout, which will further enable designers to optomize
their designs.
Loop
Grid or Mesh
Tree
Trunk
Figure 1. Clock Delay and Skew Control Layout Topologies
2
TOSHIBA Corporation
Product Brief


Part Number TC190
Description System ASIC
Maker Toshiba
Total Page 5 Pages
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TC190 pdf
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