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TEMIC Semiconductors
TEMIC Semiconductors

U208 Datasheet Preview

U208 Datasheet

Open Loop Phase Control Circuit

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U208 pdf
Open Loop Phase Control Circuit
U208B
Description
The integrated circuit, U208B, is designed as a phase con-
trol circuit in bipolar technology with internal
supply-voltage monitoring. As the voltage is built up, un-
controlled output pulses are avoided by internal
monitoring. Furthermore, it has internal-current and volt-
age synchronisation. It is recommended as a low cost
open-loop control.
Features
D Automatic retriggering
D Triggering pulse typ. 125 mA
D Voltage and current synchronisation
D Internal supply voltage monitoring
D Current requirement 2.5 mA
Package: DIP8
Block Diagram
R3
220 kW/
0.5 W
7
R4
470 kW/
0.5 W
8
Voltage Current
detector detector
Automatic
retriggering
BYT77
18 kW/
2W
D1
M
R1
L
95 11224
Output
pulse
3
R7
180 W
TIC
236N
VM =
230 V ~
R2
180 kW
R6
18 kW
100 kW
R5
120 kW
4
6
Phase
control unit
ö = f (V6)
Supply
voltage
limitation
Voltage
monitoring
10 nF
5
C2
2
–VS
1
C1
GND
22 mF/
25 V
N
Figure 1. Block diagram for simple phase control system
TELEFUNKEN Semiconductors
Rev. A1, 28-May-96
1 (7)




TEMIC Semiconductors
TEMIC Semiconductors

U208 Datasheet Preview

U208 Datasheet

Open Loop Phase Control Circuit

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U208 pdf
U208B
Description
Mains Supply
The U208B is fitted with voltage limiting and can there-
ăfore be supplied directly from the mains. The supply
voltage between Pin 1 (+ pol/ ) and Pin 2 builds up
across D1 and R1 and is smoothed by C1. The value of the
series resistance can be approximated using figure 1:
+R1
VM–VS
2 IS
Further information regarding the design of the mains
supply can be found in the data sheets in the appendix.
Operation using an externally stabilized DC voltage is not
recommended.
If the supply cannot be taken directly from the mains
because the power dissipation in R1 would be too large,
then the circuit shown in the following figure 2 should be
employed.
~
24 V~
12345
R1 C1
95 10362
Figure 2. Supply voltage for high current requirements
Phase Control
The function of the phase control is largely identical to
that of the well known component TEA1007. The phase
angle of the trigger pulse is derived by comparing the
ramp voltage, which is mains synchronized by the voltage
detector, with the nominal value predetermined at the
control input Pin 6. The slope of the ramp is determined
by C2 and its charging current. The charging current can
be varied using R2 on Pin 4. The maximum phase angle
amax can also be adjusted using R2.
When the potential on Pin 5 reaches the given value of
Pin 6, then a trigger pulse is generated whose width tp is
determined by the value of C2 (the value of C2 and hence
the pulse width can be evaluated by assuming 8 ms/nF).
The current sensor on Pin 8 ensures that, for operation
with inductive loads, no pulse will be generated in a new
half cycle as long as the current from the previous half
cycle is still flowing in the opposite direction to the sup-
ply voltage at that instant. This makes sure that ”Gaps” in
the load current are prevented. The control signal on Pin
6 can be in the range 0 V to –7 V (reference point Pin 1).
If Vpin6 = –7 V then the phase angle is at maximum = amax
i.e., the current flow angle is a minimum. The minimum
phase angle amin is when Vpin6 = Vpin1.
Voltage Monitoring
As the voltage is built up, uncontrolled output pulses are
avoided by internal voltage surveillance. At the same
time, all of the latches in the circuit are reset. Used with
a switching hysteresis of 300 mV, this system guarantees
defined start–up behavior each time the supply voltage is
switched on ,or after short interruptions of the mains
supply.
Pulse Output Stage
The pulse output stage is short circuit protected and can
typically deliver currents of 125 mA. For the design of
smaller triggering currents, the function IGT = f (RGT) has
been given in the data sheets in the appendix. In contrast
to the TEA1007, the pulse output stage of the U 208 B has
no gate bypass resistor.
Automatic Retriggering
The automatic retriggering prevents half cycles without
current flow, even if the triacs is turned off earlier e.g. due
to a collector which is not exactly centered (brush lifter)
or in the event of unsuccessful triggering. If it is neces-
sary, another triggering pulse is generated after a time
lapse of tpp = 4.5 tp and this is repeated until either the
triac fires or the half cycle finishes.
2 (7) TELEFUNKEN Semiconductors
Rev. A1, 28-May-96




TEMIC Semiconductors
TEMIC Semiconductors

U208 Datasheet Preview

U208 Datasheet

Open Loop Phase Control Circuit

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U208 pdf
U208B
General Hints and Explanation of Terms
To ensure safe and trouble–free operation, the following
points should be taken into consideration when circuits
are being constructed or in the design of printed circuit
boards.
V
Mains
Supply
95 10716
p/2 p 3/2p 2p
D The connecting lines from C2 to Pin 5 and Pin 1 should
be as short as possible, and the connection to Pin 1
should not carry any additional high current such as
e.g. the load current.
D When selecting C2, a low temperature coefficient is
desirable.
VGT
Trigger
Pulse
VL
tp
tpp = 4.5 tp
Load
Voltage
IL
Load
Current
ö
F
Figure 3. Explanation of terms in phase relationship
Absolute Maximum Ratings
Reference point Pin 1, unless otherwise specified
Parameters
Current requirement
t 10 ms
Synchronisation current
t
t
<
<
10
10
mmss
Pin 2
Pin 8
Pin 7
Pin 8
Pin 7
Phase control
Input voltage
Input current
Pin 6
Pin 6
Pin 4
Power dissipation
Tamb = 45°C
Tamb = 80°C
Storage temperature range
Junction temperature
Ambient temperature range
Symbol
–IS
–is
IsyncI
IsyncV
"iI
"iV
"–VI
II
II
Ptot
Tstg
Tj
Tamb
Value
30
100
5
5
35
35
0 to 7
500
1
530
300
–40 to +125
125
–10 to +100
Unit
mA
mA
mVA
mA
mW
°C
°C
°C
TELEFUNKEN Semiconductors
Rev. A1, 28-May-96
3 (7)




Part Number U208
Description Open Loop Phase Control Circuit
Maker TEMIC Semiconductors
Total Page 7 Pages
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