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Siemens Electronic Components Datasheet

HYB39S256160 Datasheet

(HYB39S256xxx) 256 MBit Synchronous DRAM

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HYB39S256160 pdf
256 MBit Synchronous DRAM
HYB 39S256400/800/160T
Preliminary Information
• High Performance:
-8 -8B -10 Units
fCK 125 100 100 MHz
tCK3 8 10 10 ns
tAC3
6
6
7 ns
tCK2 10 12 15 ns
tAC2
6
7
8 ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3, 4
www.DataSheet4U.com Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control (× 4, × 8)
• Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 8192 refresh cycles/64 ms 7,8 µ
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-54 400mil width (× 4, × 8, × 16)
• -8 part for PC100 2-2-2 operation
-8B part for PC100 3-2-3 operation
-10 part for PC66 2-2-2 operation
The HYB 39S256400/800/160T are four bank Synchronous DRAM’s organized as
4 banks × 16 MBit × 4, 4 banks × 8 MBit × 8 and 4 banks × 4 MBit × 16 respectively. These syn-
chronous devices achieve high speed data transfer rates for CAS latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V ± 0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01



Siemens Electronic Components Datasheet

HYB39S256160 Datasheet

(HYB39S256xxx) 256 MBit Synchronous DRAM

No Preview Available !

HYB39S256160 pdf
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Ordering Information
Type
Ordering
Code
LVTTL-Version
HYB 39S256400T-8 on request
HYB 39S256400T-8B on request
HYB 39S256400T-10 on request
HYB 39S256800T-8 on request
HYB 39S256800T-8B on request
HYB 39S256800T-10 on request
HYB 39S256800T-8 on request
HYBwww.DataSheet4U.com 39S256800T-8B on request
HYB 39S256800T-10 on request
Package
Description
P-TSOP-54-2 400 mil 125 MHz 4B × 16 M × 4 SDRAM
PC100-222-620
P-TSOP-54-2 400 mil 100 MHz 4B × 16 M × 4 SDRAM
PC100-323-620
P-TSOP-54-2 400 mil 66 MHz 4B × 16 M × 4 SDRAM
PC66-222-820
P-TSOP-54-2 400 mil 125 MHz 4B × 8 M × 8 SDRAM
PC100-222-620
P-TSOP-54-2 400 mil 100 MHz 4B × 8 M × 8 SDRAM
PC100-323-620
P-TSOP-54-2 400 mil 66 MHz 4B × 8 M × 8 SDRAM
PC66-222-820
P-TSOP-54-2 400 mil 125 MHz 4B × 4 M × 16 SDRAM
PC100-222-620
P-TSOP-54-2 400 mil 100 MHz 4B × 4 M × 16 SDRAM
PC100-323-620
P-TSOP-54-2 400 mil 66 MHz 4B × 4 M × 16 SDRAM
PC66-222-820
Pin Description and Pinouts
CLK Clock Input
CKE
Clock Enable
CS Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE Write Enable
A0 - A12
Address Inputs
BA0, BA1
Bank Select
DQ Data Input/Output
DQM, LDQM, UDQM Data Mask
VDD
VSS
VDDQ
VSSQ
NC
Power (+ 3.3 V)
Ground
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not Connected
Semiconductor Group
2
1998-10-01


Part Number HYB39S256160
Description (HYB39S256xxx) 256 MBit Synchronous DRAM
Maker Siemens Semiconductor
Total Page 30 Pages
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