
	Samsung Electronic Components Datasheet

KM6161002B Datasheet

CMOS SRAM

No Preview Available !

KM6161002B, KM6161002BI

CMOS SRAM

Document Title

64Kx16 Bit High Speed Static RAM(5.0V Operating), Revolutionary Pin out.

Operated at Commercial and Industrial Temperature Range.

Revision History

RevNo.

History

Draft Data

Remark

Rev. 0.0

Initial release with Design Target.

Apr. 1st, 1997

Design Target

Rev. 1.0

Release to Preliminary Data Sheet.

1. Replace Design Target to Preliminary.

Jun. 1st, 1997

Preliminary

Rev. 2.0

Release to Final Data Sheet.

2.1. Delete Preliminary

2.2. Delete L-version.

2.3. Delete Data Retention Characteristics and Waveform.

2.4. Add Capacitive load of the test environment in A.C test load

2.5. Change D.C characteristics

Items

Previous spec.

(8/10/12ns part)

Changed spec.

(8/10/12ns part)

Icc

200/190/180mA

200/195/190mA

Isb

30mA

50mA

Feb. 25th, 1998 Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of th is

device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

-1-

Rev 2.0

February 1998


	Samsung Electronic Components Datasheet

KM6161002B Datasheet

CMOS SRAM

No Preview Available !

KM6161002B, KM6161002BI

CMOS SRAM

64K x 16 Bit High-Speed CMOS Static RAM

FEATURES

• Fast Access Time 8,10,12ns(Max.)

• Low Power Dissipation

Standby (TTL) : 50 mA(Max.)

(CMOS) : 10 mA(Max.)

Operating KM6161002B - 8 : 200 mA(Max.)

KM6161002B - 10 : 195 mA(Max.)

KM6161002B - 12 : 190 mA(Max.)

• Single 5.0V±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16

• Standard Pin Configuration

KM6161002BJ : 44-SOJ-400

KM6161002BT : 44-TSOP2-400F

ORDERING INFORMATION

KM6161002B -8/10/12

Commercial Temp.

KM6161002BI -8/10/12

Industrial Temp.

FUNCTIONAL BLOCK DIAGRAM

Clk Gen.

Pre-Charge Circuit

I/O1~I/O8

I/O9~I/O16

Memory Array

256 Rows

256x16 Columns

Data

Cont.

Data

Cont.

Gen.

CLK

I/O Circuit &

Column Select

A8 A9 A10 A11 A12 A13 A14 A15

GENERAL DESCRIPTION

The KM6161002B is a 1,048,576-bit high-speed Static Random

Access Memory organized as 65,536 words by 16 bits. The

KM6161002B uses 16 common input and output lines and has

at output enable pin which operates faster than address access

time at read cycle. Also it allows that lower and upper byte

access by data byte control ( UB, LB). The device is fabricated

using SAMSUNG′s advanced CMOS process and designed for

high-speed circuit technology. It is particularly well suited for

use in high-density high-speed system applications. The

KM6161002B is packaged in a 400mil 44-pin plastic SOJ or

TSOP2 forward.

PIN CONFIGURATION (Top View)

A0 1

A1 2

A2 3

A3 4

A4 5

CS 6

I/O1 7

I/O2 8

I/O3 9

I/O4 10

Vcc 11

Vss 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A5 18

A6 19

A7 20

A8 21

N.C. 22

SOJ/

TSOP2

44 A15

43 A14

42 A13

41 OE

40 UB

39 LB

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 Vss

33 Vcc

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 N.C.

27 A12

26 A11

25 A10

24 A9

23 N.C.

PIN FUNCTION

Pin Name

A0 - A15

I/O1 ~ I/O16

VCC

VSS

N.C

Pin Function

Address Inputs

Write Enable

Chip Select

Output Enable

Lower-byte Control(I/O 1~I/O8)

Upper-byte Control(I/O 9~I/O16)

Data Inputs/Outputs

Power(+5.0V)

Ground

No Connection

-2-

Rev 2.0

February 1998

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KM6161002B Datasheet

CMOS SRAM

KM6161002B Datasheet

CMOS SRAM

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