| Description | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... |
| Features |
■ Fast 8-bit Turbo 8032 MCU, 40 MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40 MHz (5 V) ) – JTAG debug and in-system programming t(s – 16-bit internal instruction path fetches c double-byte instruction in a single memory u cycle rod – Branch cache & 4 instruction prefetch P t(s) queue – Dual XDATA pointers with a... |
| Datasheet |
 UPSD3422E Datasheet - 2.72MB |
