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STMicroelectronics Electronic Components Datasheet

M24164 Datasheet

16 Kbit Serial I2C BUS EEPROM

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M24164 pdf
M24164
TWO WIRE I2C SERIAL INTERFACE
SUPPORTS 400kHz PROTOCOL
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
2ms TYPICAL PROGRAMMING TIME
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for M24164
– 2.5V to 5.5V for M24164-W
– 1.8V to 5.5V for M24164-R
HARDWARE WRITE CONTROL
BYTE and PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH-UP
PERFORMANCES
16 Kbit Serial I2C BUS EEPROM
PRELIMINARY DATA
8
1
PSDIP8 (BN)
0.25mm Frame
8
1
SO8 (MN)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The M24164 is a 16 Kbit EEPROM. The memory
is an electrically erasable programmable memory
(EEPROM) fabricated with STMicroelectronics’s
High Endurance Single Polysilicon CMOS technol-
ogy which guarantees an endurance typically well
above one million erase/write cycles with a data
retention of 40 years. The "-W" version operate with
a power supply value as low as 2.5V and the "-R"
version operate down to 1.8V.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
Table 1. Signal Names
E0-E2
Chip Enable Inputs
SDA
Serial Data Address Input/Output
SCL Serial Clock
WC Write Control
VCC Supply Voltage
VSS Ground
VCC
3
E0-E2
SCL
WC
M24164
SDA
VSS
AI02264
January 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/16



STMicroelectronics Electronic Components Datasheet

M24164 Datasheet

16 Kbit Serial I2C BUS EEPROM

No Preview Available !

M24164 pdf
M24164
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
TSTG
TLEAD
Parameter
Ambient OperatingTemperature(2)
Storage Temperature
Lead Temperature, Soldering
(PSDIP8 package)
(SO8 package)
10 sec
40 sec
Value
–40 to 125
–65 to 150
260
215
Unit
°C
°C
°C
VIO Input or Output Voltages
–0.6 to 6.5
V
VCC
VESD
Supply Voltage
Electrostatic Discharge Voltage (Human Body model) (3)
Electrostatic Discharge Voltage (Machine model) (4)
–0.3 to 6.5
4000
500
V
V
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Depends on range.
3. MIL-STD-883C, 3015.7 (100pF, 1500 ).
4. EIAJ IC-121 (Condition C) (200pF, 0 ).
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
M24164
E0
E1
E2
VSS
1
2
3
4
8 VCC
7 WC
6 SCL
5 SDA
AI02265
E0
E1
E2
VSS
M24164
18
27
36
45
AI02266
VCC
WC
SCL
SDA
DESCRIPTION (cont’d)
The memory is compatible with the two wire serial
interface which uses a bi-directional data bus and
serial clock. The memory offers 3 chip enable
inputs (E2, E1, E0) so that up to 8 x 16K devices
may be attached to the bus and selected individu-
ally. The memory behaves as a slave device with
all memory operations synchronized by the serial
clock.
Read and write operations are initiated by a START
condition generated by the bus master. The START
condition is followed by a stream of 7 bits, plus one
read/write bit and terminated by an acknowledge
bit (see Table 3). When writing data to the memory
it responds to the 8 bits received by asserting an
acknowledge bit during the 9th bit time. When data
is read by the bus master, it acknowledges the
receipt of the data bytes in the same way. Data
transfers are terminated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent any possible data corruption and
inadvertent write operations during power up, a
Power On Reset (POR) circuit is implemented.
Until the VCC voltage has reached the POR thresh-
old value, the internal reset is active, all operations
are disabled and the device will not respond to any
command. In the same way, when VCC drops down
from the operating voltage to below the POR
threshold value, all operations are disabled and the
device will not respond to any command. A stable
VCC must be applied before applying any logic
signal.
2/16



STMicroelectronics Electronic Components Datasheet

M24164 Datasheet

16 Kbit Serial I2C BUS EEPROM

No Preview Available !

M24164 pdf
Table 3. Device Select Code
Bit b7
Device Select
1
Note: The MSB b7 is sent first.
b6
E2
Chip Enable
b5
E1
b4
E0
M24164
MSB Address
b3 b2
A10 A9
b1
A8
RW
b0
RW
Table 4. Operating Modes (1)
Mode
RW bit
Current Address Read
’1’
Random Address Read
’0’
’1’
Sequential Read
’1’
Byte Write
’0’
Page Write
Note: 1. X = VIH or VIL.
’0’
WP Data Bytes
Initial Sequence
X 1 START, Device Select, RW = ’1’
X START, Device Select, RW = ’0’, Address,
1
X reSTART, Device Select, RW = ’1’
X 1 As CURRENT or RANDOM Mode
VIL 1 START, Device Select, RW = ’0’
VIL
16
START, Device Select, RW = ’0’
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. Aresistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E2 - E0). These chip enable inputs
are used to set 3 bits (b6, b5, b4) of the 7 bit device
select code. These inputs may be driven dynami-
cally or tied to VCC or VSS to establish the device
select code.
Write Control (WC). A hardware Write Control pin
(WC) is provided on pin 7 of the memory. This
feature is useful to protect the entire contents of the
memory from any erroneous erase/write cycle. The
Write Control signal is used to enable (WC=VIL) or
disable (WC=VIH) write instructions to the entire
memory area. When unconnected, the WC input is
internally read as VIL and write operations are
allowed. When WC=1, Device Select and Address
bytes are acknowledged, Data bytes are not ac-
knowledged.
Refer to Application Note AN404 for more detailed
information about Write Control feature.
DEVICE OPERATION
I2C Bus Background
The memory supports the I2C protocol. This proto-
col defines any device that sends data onto the bus
as a transmitter and any device that reads the data
as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The memory is always a slave device
in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the memory continu-
ously monitors the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the memory and the
bus master. A STOP condition at the end of a Read
sequence, after and only after a No-Acknowledge,
forces the standby state. A STOP condition at the
end of a Write command triggers the internal
EEPROM write cycle.
3/16




Part Number M24164
Description 16 Kbit Serial I2C BUS EEPROM
Maker STMicroelectronics
Total Page 16 Pages
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