http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf



STMicroelectronics Electronic Components Datasheet

M14C64 Datasheet

Memory Card IC 64/32 Kbit Serial IC Bus EEPROM

No Preview Available !

M14C64 pdf
M14C64
M14C32
Memory Card IC
64/32 Kbit Serial I²C Bus EEPROM
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage (2.5 V to 5.5 V)
s Hardware Write Control
s BYTE and PAGE WRITE (up to 32 Bytes)
s BYTE, RANDOM and SEQUENTIAL READ
Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behaviour
s 1 Million Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
s 5 ms Programming Time (typical)
DESCRIPTION
Each device is an electrically erasable program-
mable memory (EEPROM) fabricated with STMi-
croelectronics’s High Endurance, Single
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of
40 years. The memory operates with a power sup-
ply as low as 2.5 V.
The M14C32 is available in wafer form (either
sawn or unsawn) and in micromodule form (on
film). The M14C64 is available in micro-module
Table 1. Signal Names
SDA
Serial Data/Address Input/
Output
SCL Serial Clock
WC Write Control
VCC
Supply Voltage
GND
Ground
Micromodule (D20)
Micromodule (D22)
Wafer
Figure 1. Logic Diagram
VCC
SCL
WC M14xxx
SDA
GND
AI02217
October 1999
1/14



STMicroelectronics Electronic Components Datasheet

M14C64 Datasheet

Memory Card IC 64/32 Kbit Serial IC Bus EEPROM

No Preview Available !

M14C64 pdf
M14C64, M14C32
Figure 2. D20 Contact Connections
VCC
WC
SCL
GND
SDA
Figure 3. D22 Contact Connections
VCC
WC
SCL
GND
SDA
AI02168
AI02204
form only. For availability of the M14C64 in wafer
form, please contact your ST sales office.
Each memory is compatible with the I2C extended
memory standard. This is a two wire serial inter-
face that uses a bi-directional data bus and serial
clock. The memory carries a built-in 7-bit unique
Device Type Identifier code (1010000) in accord-
ance with the I2C bus definition. Only one memory
can be attached to each I2C bus.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by
the Device Select Code which is composed of a
stream of 7 bits (1010000), plus one read/write bit
(R/W) and is terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoACK for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the VCC voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
Table 2. Absolute Maximum Ratings 1
Symbol
Parameter
Value
Unit
TA Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature
Wafer form
Module form
-65 to 150
-40 to 120
°C
VIO Input or Output range
-0.6 to 6.5
V
VCC Supply Voltage
-0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
Electrostatic Discharge Voltage (Machine model) 3
4000
400
V
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
3. EIAJ IC-121 (Condition C) (200 pF, 0 )
2/14



STMicroelectronics Electronic Components Datasheet

M14C64 Datasheet

Memory Card IC 64/32 Kbit Serial IC Bus EEPROM

No Preview Available !

M14C64 pdf
M14C64, M14C32
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to synchronize all data
in and out of the memory. A pull up resistor can be
connected from the SCL line to VCC. (Figure 4 in-
dicates how the value of the pull-up resistor can be
calculated).
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 4 indicates how the value of the
pull-up resistor can be calculated).
Write Control (WC)
The hardware Write Control contact (WC) is useful
for protecting the entire contents of the memory
from inadvertent erase/write. The Write Control
signal is used to enable (WC=VIL) or disable
(WC=VIH) write instructions to the entire memory
area. When unconnected, the WC input is internal-
ly read as VIL and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the XI2C (Extended
I2C) protocol, as summarized in Figure 5. Any de-
vice that sends data on to the bus is defined to be
a transmitter, and any device that reads the data
to be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can only be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoACK, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
sending 8 bits of data. During the 9th clock pulse
period the receiver pulls the SDA bus low to ac-
knowledge the receipt of the 8 data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
20
16
12
8
4
0
10
fc = 100kHz
fc = 400kHz
100
CBUS (pF)
SDA
MASTER
SCL
RL
RL
CBUS
1000
CBUS
AI01665
3/14




Part Number M14C64
Description Memory Card IC 64/32 Kbit Serial IC Bus EEPROM
Maker STMicroelectronics
Total Page 14 Pages
PDF Download
M14C64 pdf
Download PDF File
M14C64 pdf
View for Mobile






Related Datasheet

1 M14C64 Memory Card IC 64/32 Kbit Serial IC Bus EEPROM STMicroelectronics
STMicroelectronics
M14C64 pdf
2 M14C64 Memory Micromodules General Information for D1/ D2 and C Packaging STMicroelectronics
STMicroelectronics
M14C64 pdf




Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components