Write Control (WC)
The hardware Write Control contact (WC) is useful
for protecting the entire contents of the memory
from inadvertent erase/write. The Write Control
signal is used to enable (WC=VIL) or disable
(WC=VIH) write instructions to the entire memory
area. When unconnected, the WC input is internal-
ly read as VIL and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
The memory device supports the XI2C (Extended
I2C) protocol, as summarized in Figure 4. Any de-
vice that sends data on to the bus is defined to be
a transmitter, and any device that reads the data
to be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can only be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
STOP is identified by a low to high transition of the
SDA line while the clock, SCL, is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoACK, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
sending 8 bits of data. During the 9th clock pulse
period the receiver pulls the SDA bus low to ac-
knowledge the receipt of the 8 data bits.
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW bit.
The seven most significant bits of the Device Se-
lect Code are the Device Type Identifier, according
to the I2C bus definition. For the memory device,
the seven bits are fixed at 1010000b (A0h), as
shown in Table 5.
The 8th bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
fc = 100kHz
fc = 400kHz