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STMicroelectronics Electronic Components Datasheet

M14256 Datasheet

Memory Card IC 256/128 Kbit Serial IC Bus EEPROM

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M14256 pdf
M14256
M14128
Memory Card IC
256/128 Kbit Serial I²C Bus EEPROM
PRELIMINARY DATA
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage (2.5 V to 5.5 V)
s Hardware Write Control
s BYTE and PAGE WRITE (up to 64 Bytes)
s BYTE, RANDOM and SEQUENTIAL READ
Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behaviour
s 100,000 Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
s 5 ms Programming Time (typical)
Micromodule (D22)
DESCRIPTION
Each device is an electrically erasable program-
mable memory (EEPROM) fabricated with STMi-
croelectronics’s High Endurance, Double
Polysilicon, CMOS technology. This guarantees
an endurance typically well above 100,000 Erase/
Write cycles, with a data retention of 40 years. The
memory operates with a power supply as low as
2.5 V.
The M14256 and M14128 are available in micro-
module form only. For availability of the M14256 or
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
SDA
Serial Data/Address Input/
Output
SCL Serial Clock
WC Write Control
VCC
Supply Voltage
GND
Ground
SCL SDA
WC M14xxx
GND
AI02217
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/12



STMicroelectronics Electronic Components Datasheet

M14256 Datasheet

Memory Card IC 256/128 Kbit Serial IC Bus EEPROM

No Preview Available !

M14256 pdf
M14256, M14128
Figure 2. D22 Contact Connections
VCC
WC
SCL
GND
SDA
AI02204
M14128 in wafer form, please contact your ST
sales office.
Each memory device is compatible with the I2C
extended memory standard. This is a two wire se-
rial interface that uses a bi-directional data bus
and serial clock. The memory device carries a
built-in 7-bit unique Device Type Identifier code
(1010000) in accordance with the I2C bus defini-
tion. Only one memory device can be attached to
each I2C bus.
The memory device behaves as a slave device in
the I2C protocol, with all memory operations syn-
chronized by the serial clock. Read and write op-
erations are initiated by a START condition,
generated by the bus master. The START condi-
tion is followed by the Device Select Code which is
composed of a stream of 7 bits (1010000), plus
one read/write bit (R/W) and is terminated by an
acknowledge bit.
When writing data to the memory, the memory de-
vice inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoACK for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the VCC voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to synchronize all data
in and out of the memory. A pull up resistor can be
connected from the SCL line to VCC. (Figure 3 in-
dicates how the value of the pull-up resistor can be
calculated).
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Table 2. Absolute Maximum Ratings 1
Symbol
Parameter
Value
Unit
TA Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature
-40 to 120
°C
VIO Input or Output range
-0.6 to 6.5
V
VCC Supply Voltage
-0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
Electrostatic Discharge Voltage (Machine model) 3
4000
400
V
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
3. EIAJ IC-121 (Condition C) (200 pF, 0 )
2/12



STMicroelectronics Electronic Components Datasheet

M14256 Datasheet

Memory Card IC 256/128 Kbit Serial IC Bus EEPROM

No Preview Available !

M14256 pdf
M14256, M14128
Write Control (WC)
The hardware Write Control contact (WC) is useful
for protecting the entire contents of the memory
from inadvertent erase/write. The Write Control
signal is used to enable (WC=VIL) or disable
(WC=VIH) write instructions to the entire memory
area. When unconnected, the WC input is internal-
ly read as VIL and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the XI2C (Extended
I2C) protocol, as summarized in Figure 4. Any de-
vice that sends data on to the bus is defined to be
a transmitter, and any device that reads the data
to be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can only be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock, SCL, is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoACK, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
sending 8 bits of data. During the 9th clock pulse
period the receiver pulls the SDA bus low to ac-
knowledge the receipt of the 8 data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW bit.
The seven most significant bits of the Device Se-
lect Code are the Device Type Identifier, according
to the I2C bus definition. For the memory device,
the seven bits are fixed at 1010000b (A0h), as
shown in Table 5.
The 8th bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
20
16
12
8
4
0
10
fc = 100kHz
fc = 400kHz
100
CBUS (pF)
SDA
MASTER
SCL
RL
RL
CBUS
1000
CBUS
AI01665
3/12




Part Number M14256
Description Memory Card IC 256/128 Kbit Serial IC Bus EEPROM
Maker STMicroelectronics
Total Page 12 Pages
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