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  ON Semiconductor Electronic Components Datasheet  

NB6L239 Datasheet

2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider

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NB6L239 pdf
NB6L239
2.5V / 3.3V Any Differential
Clock IN to Differential
LVPECL OUT ÷1/2/4/8,
÷2/4/8/16 Clock Divider
Description
The NB6L239 is a highspeed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive a pair of differential
LVPECL outputs. (More device information on page 7). The
NB6L239 is a member of the ECLinPS MAXFamily of the high
performance clock products.
Features
Maximum Clock Input Frequency, 3.0 GHz
CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL/HCSL
EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS
Rise/Fall Time 65 ps Typical
< 10 ps Typical OutputtoOutput Skew
Example: 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
Internal 50 W Termination Provided
Random Clock Jitter < 1 ps RMS
QA B1 Edge Aligned to QBBn Edge
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
Master Reset for Synchronization of Multiple Chips
VBBAC Reference Output
Synchronous Output Enable/Disable
These Devices are PbFree and are RoHS Compliant
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB6L
239
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
SELA0
SELA1
CLK
VT 50 W
50 W
CLK
B1
A
B2
B4
B8
QA
QA
VBBAC
EN
SELB0
SELB1
MR
+
B2
B B4
B8
B16
Figure 1. Simplified Logic Diagram
QB
QB
© Semiconductor Components Industries, LLC, 2013
January, 2013 Rev. 6
1
Publication Order Number:
NB6L239/D


  ON Semiconductor Electronic Components Datasheet  

NB6L239 Datasheet

2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider

No Preview Available !

NB6L239 pdf
NB6L239
MR SELA0 SELA1 VCC
16 15 14 13
VT 1
12 QA
CLK 2
CLK 3
NB6L239
11 QA
10 QB
VBBAC 4
9 QB
5678
EN SELB0 SELB1 VEE
Exposed Pad (EP)
Figure 2. Pinout: QFN16 (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
1 VT
2 CLK LVPECL, CML, LVDS,
HCSL, HSTL Input
3 CLK LVPECL, CML, LVDS,
HCSL, HSTL Input
4 VBBAC
5 EN* LVCMOS/LVTTL Input
6
SELB0*
LVCMOS/LVTTL Input
7
SELB1*
LVCMOS/LVTTL Input
8 VEE
9 QB
Power Supply
LVPECL Output
10 QB
LVPECL Output
11 QA
LVPECL Output
12 QA
LVPECL Output
13 VCC
Power Supply
14 SELA1* LVCMOS/LVTTL Input
15 SELA0* LVCMOS/LVTTL Input
16 MR** LVCMOS/LVTTL Input
EP Power Supply (OPT)
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
Description
Internal 100 W CenterTapped Termination Pin for CLK and CLK.
Noninverted Differential CLOCK Input.
Inverted Differential CLOCK Input.
Output Voltage Reference for Capacitor Coupled Inputs, Only.
Synchronous Output Enable
Clock Divide Select Pin
Clock Divide Select Pin
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
Noninverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
Inverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
Noninverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
Positive Supply Voltage.
Clock Divide Select Pin
Clock Divide Select Pin
Master Reset Asynchronous, Default Open High, Asserted LOW
The Exposed Pad on the QFN16 package bottom is thermally connected to the die for
improved heat transfer out of package. The pad is electrically connected to the die, and
is recommended to be electrically and thermally connected to VEE on the PC board.
http://onsemi.com
2


Part Number NB6L239
Description 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider
Maker ON Semiconductor
Total Page 12 Pages
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