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  ON Semiconductor Electronic Components Datasheet  

NB6L11 Datasheet

2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL

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NB6L11 pdf
NB6L11
2.5V/3.3V Multilevel Input to
Differential LVPECL/LVNECL
1:2 Clock or Data
Fanout Buffer/Translator
The NB6L11 is an enhanced differential 1:2 clock or data fanout
buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.
Differential input can be configured to accept single−ended signal
by applying an external reference voltage to unused complimentary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.
Maximum Input Clock Frequency w 6 GHz Typical
Maximum Input Data Rate w 6 Gb/s Typical
Low 14 mA Typical Power Supply Current
150 ps Typical Propagation Delay
5 ps Typical Within Device Skew
75 ps Typical Rise/Fall Times
PECL Mode Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.465 V
Open Input Default State
Q Outputs Will Default LOW with Inputs Open or at VEE
LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input
Compatible
http://onsemi.com
8
1
SO−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
8
6L11
ALYW
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
6L11
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping
NB6L11D
SO−8 98 Units/Rail
NB6L11DR2
SO−8
2500/
Tape & Reel
NB6L11DT**
TSSOP−8 100 Units/Rail
NB6L11DTR2**
TSSOP−8
2500/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
**Future Product − Contact factory for availability.
Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 2
1
Publication Order Number:
NB6L11/D


  ON Semiconductor Electronic Components Datasheet  

NB6L11 Datasheet

2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL

No Preview Available !

NB6L11 pdf
NB6L11
Q0 1
8 VCC
Q0 2
Q1 3
R2 7
R1
D
R1 6
R2
D
Q1 4
5 VEE
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin Name
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 Q0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ2 Q0
I/O
ECL Output
ECL Output
Default State
Description
Non−inverted differential clock/data output 0. Typically
terminated with 50 W Resistor to VTT = VCC − 2 V.
Inverted differential clock/data output 0. Typically termi-
nated with 50 W resistor to VTT = VCC − 2 V.
3 Q1
ECL Output
− Non−inverted differential clock/data output 1. Typically
terminated with 50 W resistor to VTT = VCC − 2 V.
4 Q1
ECL Output
− Inverted differential clock/data output 1. Typically termi-
nated with 50 W resistor to VTT = VCC − 2 V.
5 VEE
− − Negative power supply voltage
6
D
LVDS, CML, LVPECL,
HIGH
Inverted differential clock/data input. Internal 37.5 kW to
LVNECL, LVCMOS,
LVTTL Input
VCC and 75 kW to VEE.
7
D
LVDS, CML, LVPECL,
LOW
Non−inverted differential clock/data input. Internal
LVNECL, LVCMOS,
LVTTL Input
75 kW to VCC and 37.5 kW to VEE.
8 VCC
− − Positive power supply voltage
Table 2. ATTRIBUTES
Characteristics
Internal Input Default State Resistor
Internal Input Default State Resistor
ESD Protection
(R1)
(R2)
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
37.5 kW
75 kW
> 2 kV
> 100 V
> 1 kV
Level 1
UL 94 V−0 @ 0.125 in
167
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2


Part Number NB6L11
Description 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL
Maker ON Semiconductor
Total Page 12 Pages
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