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  ON Semiconductor Electronic Components Datasheet  

NB3H63143G Datasheet

Programmable Clock Generator

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NB3H63143G pdf
NB3H63143G
Programmable Clock
Generator with Single Ended
(LVCMOS/LVTTL) and
Differential (LVPECL/LVDS/
HCSL/CML) Outputs
www.onsemi.com
The NB3H63143G is a one−time programmable (OTP), low power
PLL−based clock generator that supports any output frequency from
8 kHz to 200 MHz. The device accepts fundamental mode parallel
resonant crystal or a single ended (LVCMOS/LVTTL) reference clock
as input. It generates either three single ended (LVCMOS/LVTTL)
1
QFN16
CASE 485AE
outputs, or one single ended output and one differential
(LVPECL/LVDS/HCSL/CML) output. The output signals can be
MARKING DIAGRAM
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Individual output enable pins OE[2:0] are available to enable/disable
3H631
43Gxx
ALYWG
G
the outputs. Individual output voltage pins VDDO[2:0] are available
to independently set the output voltage of each output. Up to four
different configurations can be written into the device memory. Two
selection pins (SEL[1:0]) allow the user to select the configuration to
use. Using the PLL bypass mode, it is possible to get a copy of the
input clock on any or all of the outputs. The device can be powered
down using the Power Down pin (PD#). It is possible to program the
internal input crystal load capacitance and the output drive current
3H63143G
xx
A
L
Y
W
G
= Specific Device Code
= Specific Program Code (Default
‘00’ for Unprogrammed Part)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
provided by the device. The device also has automatic gain control
(Note: Microdot may be in either location)
(crystal power limiting) circuitry which avoids the device overdriving
the external crystal.
Features
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
Operating Power Supply: 3.3 V ±10%, 2.5 V ±10%
I/O Standards
Programmable Output Drive Current for Single Ended
Inputs: LVCMOS/LVTTL, Fundamental Mode
Outputs
Crystal
Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL
Outputs: LVPECL, LVDS, HCSL and CML
3 Programmable Single Ended (LVCMOS/LVTTL)
Outputs from 8 kHz to 200 MHz
1 Programmable Differential Clock Output up to
200 MHz
Input Frequency Range
Crystal: 3 MHz to 50 MHz
Power Saving Mode through Power Down Pin
Programmable PLL Bypass Mode
Programmable Output Inversion
Programming and Evaluation Kit Available for Field
Programming and Quick Evaluation
Temperature Range −40°C to 85°C
Packaged in 16−pin QFN
These are Pb−Free Devices
Reference Clock: 3 MHz to 200 MHz
Configurable Spread Spectrum Frequency Modulation
Typical Applications
eBooks and Media Players
Parameters (Type, Deviation, Rate)
Individual Output Enable Pins
Independent Output Voltage Pins
Smart Wearables, Smart Phones, Portable Medical and
Industrial Equipment
Set Top Boxes, Printers, Digital Cameras and
Programmable Internal Crystal Load Capacitors
Camcorders
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 2
1
Publication Order Number:
NB3H63143G/D


  ON Semiconductor Electronic Components Datasheet  

NB3H63143G Datasheet

Programmable Clock Generator

No Preview Available !

NB3H63143G pdf
NB3H63143G
BLOCK DIAGRAM
VDD PD# SEL0 SEL1
Reference XIN/ CLKIN
Clock
Crystal
XOUT
Input
Decoder
Crystal/Clock Control
Clock Buffer/
Crystal
Oscillator And
AGC
PLL Block
Phase
Detector
Configuration
Memory
Frequency
and SS
Output control
Output
Divider
Charge
Pump
Feedback
Divider
VCO
Output
Divider
PLL Bypass Mode
Output
Divider
CMOS/
DIFF
buffer
CMOS/
DIFF
buffer
CMOS
buffer
VDDO0
CLK0
OE0
VDDO1
CLK1
OE1
VDDO2
CLK2
OE2
GND GNDO
Notes:
1. CLK0 and CLK1 can be configured to be one LVPECL, LVDS, HCSL or CML output, or two single ended LVCMOS/LVTTL outputs.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. OE[2:0], SEL[1:0] have internal pull up resistors. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
XIN/CLKIN 1
16 15 14 13
NB3H63143G
12 VDD
XOUT 2
PD# 3
GNDO
(EPAD)
11 VDDO1
10 CLK1
GND 4
9 CLK0
5 67 8
Figure 2. Pin Connections (Top View) − QFN16 (with EPAD)
www.onsemi.com
2


Part Number NB3H63143G
Description Programmable Clock Generator
Maker ON Semiconductor
Total Page 24 Pages
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