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NB2304A Datasheet

Zero Delay Clock Buffer

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NB2304A
3.3 V Zero Delay
Clock Buffer
The NB2304A is a versatile, 3.3 V zero delay buffer designed to
distribute highspeed clocks in PC, workstation, datacom, telecom
and other highperformance applications. It is available in an 8 pin
package. The part has an onchip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be driven
to FBK pin, and can be obtained from one of the outputs. The
inputtooutput propagation delay is guaranteed to be less than
250 ps, and the outputtooutput skew is guaranteed to be less than
200 ps.
The NB2304A has two Banks of two outputs each. Multiple
NB2304A devices can accept the same input clock and distribute it. In
this case, the skew between the outputs of the two devices is
guaranteed to be less than 500 ps.
The NB2304A is available in two different configurations (Refer to
NB2304A Configurations Table). The NB2304Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2304Ax1H is the highdrive version of
the 1 and the rise and fall times on this device are much faster.
The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X
frequencies on each output Bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
Features
Zero Input Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations Refer to NB2304A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple LowSkew Outputs
OutputOutput Skew < 200 ps
DeviceDevice Skew < 500 ps
Two Banks of Four Outputs
Less than 200 ps CycletoCycle Jitter (1, 1H, 5H)
Available in Space Saving, 8 pin 150 mil SOIC Package
3.3 V Operation
Advanced 0.35 m CMOS Technology
Industrial Temperature Available
These are PbFree Devices
http://onsemi.com
8
1
SOIC8
D SUFFIX
CASE 751
MARKING
DIAGRAM*
8
XXXX
ALYW
G
1
XXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 5
1
Publication Order Number:
NB2304A/D


  ON Semiconductor Electronic Components Datasheet  

NB2304A Datasheet

Zero Delay Clock Buffer

No Preview Available !

NB2304A pdf
NB2304A
FBK
REF
CLKA1
PLL
CLKA2
B2 Extra Divider (2)
CLKB1
Figure 1. Basic Block Diagram
(see Figures 11 and 12 for device specific Block Diagrams)
CLKB2
Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial)
Device
Feedback From
Bank A Frequency
NB2304Ax1
Bank A or Bank B
Reference
NB2304Ax1H
Bank A or Bank B
Reference
NB2304Ax2
Bank A
Reference
NB2304Ax2
Bank B
2 X Reference
Bank B Frequency
Reference
Reference
Reference B2
Reference
REF 1
CLKA1 2
CLKA2 3
GND 4
NB2304A
8 FBK
7 VDD
6 CLKB2
5 CLKB1
Figure 2. Pin Configuration
Table 2. PIN DESCRIPTION
Pin # Pin Name
Description
1 REF (Note 1) Input reference frequency, 5 V
tolerant input.
2 CLKA1 (Note 2) Buffered clock output, Bank A.
3 CLKA2 (Note 2) Buffered clock output, Bank A.
4
GND
Ground.
5 CLKB1 (Note 2) Buffered clock output, Bank B.
6 CLKB2 (Note 2) Buffered clock output, Bank B.
7 VDD 3.3 V supply.
8 FBK PLL feedback input.
1. Weak pulldown.
2. Weak pulldown on all outputs.
http://onsemi.com
2


Part Number NB2304A
Description Zero Delay Clock Buffer
Maker ON Semiconductor
Total Page 10 Pages
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