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  ON Semiconductor Electronic Components Datasheet  

NB100LVEP17 Datasheet

Quad Differential Driver/Receiver

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NB100LVEP17 pdf
NB100LVEP17
2.5V / 3.3V Quad Differential
Driver/Receiver
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
Features
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
250 ps Typical Propagation Delay
Low Profile QFN Package
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.8 V
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAMS*
TSSOP−20
DT SUFFIX
CASE 948E
N100
VP17
ALYWG
G
24 1
24 PIN QFN
MN SUFFIX
CASE 485L
24
1
N100
VP17
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 8
1
Publication Order Number:
NB100LVEP17/D


  ON Semiconductor Electronic Components Datasheet  

NB100LVEP17 Datasheet

Quad Differential Driver/Receiver

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NB100LVEP17 pdf
NB100LVEP17
D0
R1
D0
R1
D1
R1
D1
R1
R2
R2
Q0
Q0
Q1
Q1
D2
R1
D2
R1
D3
R1
D3
R1
Q2
R2
Q2
Q3
R2
Q3
Figure 1. Logic Diagram
VCC
VEE
VBB
Table 1. PIN DESCRIPTION
Pin
TSSOP
QFN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1,20 13,18,21,
Name
VCC
22,23
Default
I/O State
Description
− − Positive Supply Voltage. All VCC Pins Must be Externally Connected
to Power Supply to Guarantee Proper Operation.
11 10 VEE − − Negative Supply Voltage. All VEE Pins Must be Externally Con-
nected to Power Supply to Guarantee Proper Operation.
10
2,4,6,8
3,5,7,9
9
1,3,5,7
2,4,6,8
19,17,15,13
18,16,14,12
N/A
12,15,17,2
0
11,14,16,1
9
24
VBB
D[0:3]
D[0:3]
Q[0:3]
Q[0:3]
NC
ECL Input
ECL Input
ECL Output
ECL Output
Low
High
ECL Reference Voltage Output.
Noninverted Differential Inputs [0:3]. Internal 75 kW to VEE.
Inverted Differential Inputs [0:3]. Internal 75 kW to VEE and 37 kW to
VCC.
Noninverted Differential Outputs [0:3]. Typically Terminated with
50 W to VTT = VCC − 2 V.
Inverted Differential Outputs [0:3]. Typically Terminated with 50 W to
VTT = VCC − 2 V.
No Connect. The NC Pin is Electrically Connected to the Die and
“MUST BE” Left Open.
N/A
− EP
Exposed Pad. (Note 1)
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad
on the package bottom (see case drawing) must be attached to a heat−sinking conduit.
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2


Part Number NB100LVEP17
Description Quad Differential Driver/Receiver
Maker ON Semiconductor
Total Page 10 Pages
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