http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




National Semiconductor Electronic Components Datasheet

LM2507 Datasheet

Low Power Mobile Pixel Link (MPL) Level 0 / 16-bit CPU Display interface Serializer and Deserializer

No Preview Available !

LM2507 pdf
August 2006
LM2507
Low Power Mobile Pixel Link (MPL) Level 0, 16-bit CPU
Display interface Serializer and Deserializer
General Description
The LM2507 device adapts i80 CPU style display interfaces
to the Mobile Pixel Link (MPL) Level zero serial link. When
using smart CPU type interfaces, two chip selects support a
main and sub display. A mode pin configures the device as a
Master (MST) or Slave (SLV) so the same chip can be used
on both sides of the interface.
The interconnect is reduced from 21 signals to only 3 active
signals with the LM2507 chipset easing flex interconnect
design, size constraints and cost.
The LM2507 in MST mode resides beside an application,
graphics or baseband processor and translates a parallel
bus from LVCMOS levels to serial Mobile Pixel Link levels for
transmission over a flex cable (or coax) and PCB traces to
the SLV located near the display module(s).
When the Power_Down (PD*) input is asserted on the Mas-
ter, the MDn and MC line drivers are powered down to save
current. The Slave is controlled by a separate Power_Down
input.
The LM2507 implements the physical layer of the MPL Level
0 Standard (MPL-0) and a 150 µA IB current (Class 0).
Features
n CPU Display Interface support up to
800 x 300 12SVGA formats
n Dual displays supported – CS1* & CS2*
n MPL-Level 0 Physical Layer using two data and one
clock signal
n Low Power Consumption
n Pinout mirroring enables straight through layout with
minimal vias
n Level translation between host and display
n Link power down mode reduces quiescent power
under < 10 µA
n 1.74V to 2.0V core / analog supply voltage range
n 1.74V to 3.0V I/O supply voltage range
System Benefits
n Small Interface
n Low Power
n Low EMI
n Intrinsic Level Translation
Typical Application Diagram - CPU Mode
www.DataSheet4U.com
© 2006 National Semiconductor Corporation DS201860
20186001
www.national.com


National Semiconductor Electronic Components Datasheet

LM2507 Datasheet

Low Power Mobile Pixel Link (MPL) Level 0 / 16-bit CPU Display interface Serializer and Deserializer

No Preview Available !

LM2507 pdf
Pin Descriptions — CPU
Description
Pin Name
No.
I/O, Type
CPU Master
CPU Slave
of Pins
(MST)
(SLV)
MPL SERIAL BUS PINS
MD[1:0]
2
IO, MPL MPL Data Line Driver/Receiver
MPL Data Receiver/Line Driver
MC 1 IO, MPL MPL Clock Line Driver
MPL Clock Receiver
VSSA
Ground MPL Ground - see Power/Ground Pins
CONFIGURATION/PARALLEL BUS PINS
CPU
1
I, CPU mode configuration input
LVCMOS Tie High
M/S*
1
I, Tie High for Master
Tie Low for Slave
LVCMOS
TM 1
I, Test Mode control input
LVCMOS Tie Low for normal mode (High reserved for factory test)
Mode
1
I, CPU Mode input
LVCMOS Tie High for i80 mode
CSL*/IDR
1
I, Local Chip Select input,
Insert Dummy Read control input,
LVCMOS Reserved - Tie High.
H = inserts dummy read cycle in all
READ transactions
L = uses one READ cycle for every
READ transaction
CLOCK / POWER DOWN SIGNALS
CLK
1
I, CLK input
NA
LVCMOS
PD* 1
I, Power Down input,
LVCMOS L = Powered down (sleep mode)
H = active mode
PARALLEL INTERFACE SIGNALS
D[15:0]
16
IO, CPU Data Bus inputs / outputs
CPU Data Bus outputs / inputs
LVCMOS
MF0
1
IO, Multi Function input -
Multi Function output -
(RD*)
LVCMOS Read input (RD*) for i80 I/F
Read output (RD*) for i80 I/F
MF1
1
IO, Multi Function input -
Multi Function output -
(WR*)
LVCMOS Write input (WR*) for i80 I/F
Write output (WR*) for i80 I/F
CS1*
1
IO, Chip Select One input
Chip Select One output
LVCMOS Active Low
Active Low
CS2*
1
IO, Chip Select Two input
Chip Select Two output
LVCMOS Active Low
Active Low
A/D 1
IO, Address / Data selector input
Address / Data selector output
LVCMOS
INTR/8-bit
1
IO, Interrupt Output
8-bit Mode Input
LVCMOS Active High, is asserted when READ
Tie Low for 16-bit mode
data is ready and de-asserted upon send 8-bit mode is reserved.
READ cycle OPTIONAL
www.DataSheet4U.com
www.national.com
2


Part Number LM2507
Description Low Power Mobile Pixel Link (MPL) Level 0 / 16-bit CPU Display interface Serializer and Deserializer
Maker National Semiconductor
Total Page 22 Pages
PDF Download
LM2507 pdf
Download PDF File
LM2507 pdf
View for Mobile



Buy Electronic Components




Related Datasheet

1 LM250 ADJUSTABLE VOLTAGE REGULATORS THREE-TERMINAL 3 A STMicroelectronics
STMicroelectronics
LM250 pdf
2 LM25005 LM25005 42V 2.5A Step-Down Switching Regulator (Rev. C) Texas Instruments
Texas Instruments
LM25005 pdf
3 LM25005 STEP-DOWN SWITCHING REGULATOR National Semiconductor
National Semiconductor
LM25005 pdf
4 LM25007 LM25007 42V 0.5A Step-Down Switching Regulator (Rev. C) Texas Instruments
Texas Instruments
LM25007 pdf
5 LM25007 Step-Down Switching Regulator National Semiconductor
National Semiconductor
LM25007 pdf
6 LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer National Semiconductor
National Semiconductor
LM2501 pdf
7 LM25010 LM25010/LM25010Q 42V 1.0A Step-Down Switching Regulator (Rev. D) Texas Instruments
Texas Instruments
LM25010 pdf
8 LM25010 Step-Down Switching Regulator National Semiconductor
National Semiconductor
LM25010 pdf
9 LM25010-Q1 LM25010/LM25010Q 42V 1.0A Step-Down Switching Regulator (Rev. D) Texas Instruments
Texas Instruments
LM25010-Q1 pdf






Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components